Intel BXM80530B866512 Datový list stáhnout pdf (Strana 32)

Mobile Intel

Pentium

III Processor in BGA2 and Micro-PGA2 Packages at 1 GHz,

900 MHz, 850 MHz, 800 MHz, 750 MHz, 700 MHz, Low-voltage 750 MHz, Low-voltage 700 MHz,

Low-voltage 600 MHz, Ultra Low-voltage 600 MHz and Ultra Low-voltage 500 MHz

32 Datasheet 283653-002

3.7 AC Specifications

3.7.1 System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC

Specifications

Table 13 through Table 21 provide AC specifications associated with the mobile Pentium III

processor. The AC specifications are divided into the following categories: Table 13 contains the

system bus clock specifications; Table 14 contains the processor core frequencies; Table 15

contains the GTL+ specifications; Table 16 contains the CMOS and Open-drain signal groups

specifications; Table 17 contains timings for the reset conditions; Table 18 contains the APIC

specifications; Table 19 contains the TAP specifications; and Table 20 and Table 21 contain the

power management timing specifications.

All system bus AC specifications for the GTL+ signal group are relative to the rising edge of the

BCLK input at 1.25V. All GTL+ timings are referenced to V

REF

for both “0” and “1” logic levels

unless otherwise specified. All APIC, TAP, CMOS, and Open-drain signals except PWRGOOD

are referenced to 0.75V.

Table 13. System Bus Clock AC Specifications

= 0°C to 100°C; T

= 5°C to 100°C for Vcc = 1.15V; V

= 0.975V ±25 mV or 1.10V ±80 mV or 1.15V

±80 mV or 1.35V ±100 mV or 1.60V ±115 mV or 1.70V -80/+125 mV ; V

CCT

= 1.50V ±115 mV

Symbol Parameter Min Typ Max Unit Figure Notes

System Bus Frequency 100 MHz

T1 BCLK Period 10 ns Figure 7 Note 2

T2 BCLK Period Stability ±250 ps Notes 3, 4

T3 BCLK High Time 2.70 ns Figure 7 at>2.0V

T4 BCLK Low Time 2.45 ns Figure 7 at<0.5V

T5 BCLK Rise Time 0.175 0.875 ns Figure 7 (0.9V – 1.6V)

T6 BCLK Fall Time 0.175 0.875 ns Figure 7 (1.6V – 0.9V)

NOTES:

1. All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V. All CMOS

signals are referenced at 0.75V.

2. The BCLK period allows a +0.5 ns tolerance for clock driver variation.

3. Not 100% tested. Specified by design/characterization.

4. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a

component of BCLK skew between devices.

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 85 86

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Flowserve ERPN-M Uživatelský manuál (37 strany)

Značka: Flowserve | Kategorie: Pumps | Velikost: 0.65 MB |

Tabulka s obsahem

USER INSTRUCTIONS

1.6 Safety

HOT AND COLD PARTS

1.7 Warning label

1.9 Noise level

Page 11 of 37

2.0 TRANSPORT AND STORAGE

2.2 Handling

2.3 Lifting

4.3 Foundation

4.0 INSTALLATION

4.1 Location

4.2 Part Assemblies

4.4 Initial alignment

4.5 Piping

4.6 Electrical connections

5.0 COMMISSIONING START-UP

OPERATION AND SHUTDOWN

5.2 Pump Lubricants

6.0 MAINTENANCE

6.1 General

6.2 Maintenance schedule

6.3 Spare parts

6.4 Recommended spares

6.5 Fastener torques

6.7 Disassembly

6.8 Examination of parts

6.9 Assembly

7.0 AUXILIARIES

7.1 Secondary Seal

7.3 Seal and seal systems

9.0 CERTIFICATION

10.0 OTHER RELEVANT

DOCUMENTATION AND MANUALS

10.2 Change notes

10.4 Abbreviations

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