Intel AV8062700837205 Datový list

5th Generation Intel® Core™Processor Family, Intel® Core™ MProcessor Family, Mobile Intel®Pentium® Processor Family, andMobile Intel® Celeron® Process

1.0 IntroductionThe 5th Generation Intel® Core™ processor family based on U-Processor line, Intel®Core™ M processor family, Mobile Intel® Pentium® pr

Signal Name(LP-DDR3)Ball #SA_DQ41 BR2SA_DQ42 BN6SA_DQ43 BN4SA_DQ44 BR6SA_DQ45 BR4SA_DQ46 BM5SA_DQ47 BM3SB_DQ0 BK3SB_DQ1 BK5SB_DQ2 BG6SB_DQ3 BJ2SB_DQ4

Signal Name(LP-DDR3)Ball #SA_DQSN4 BV3SA_DQSN5 BP3SB_DQSN0 BH5SB_DQSN1 BD5SB_DQSN4 AK2SB_DQSN5 AF2SA_DQSN2 CR24SA_DQSN3 CR20SA_DQSN6 BV9SA_DQSN7 BP9SB

Signal Name(LP-DDR3)Ball #SUSWARN# /SUSPWRDNACK /GPIO30D8ACPRESENT /GPIO31M17CLKRUN# / GPIO32 B35DEVSLP0 / GPIO33 E30SATA0GP / GPIO34 F29SATA1GP /SATA

Signal Name(LP-DDR3)Ball #RSVD CL28RSVD C5BPM#0 CM39BPM#1 CN38BPM#2 CK36BPM#3 CM37BPM#4 CN36BPM#5 CR35BPM#6 CN34BPM#7 CR34CL_CLK D23CL_DATA H23CL_RST#

Signal Name(LP-DDR3)Ball #SATA_Rp1 /PERp6_L2T39SATA_Rp2 /PERp6_L1W39SATA_Rp3 /PERp6_L0Y36SATA_Tn0 /PETn6_L3W43SATA_Tn1 /PETn6_L2T43SATA_Tn2 /PETn6_L1T

Signal Name(LP-DDR3)Ball #VCCACLKPLL AK35VCCCLK3 AJ28VCCCLK1 AK23VCC1_05 AG45VCC1_05 AH36VCC1_05 AJ16VCC1_05 AJ45VCC1_05 T17VCC1_05 W22VCC1_05 Y22DCPS

Signal Name(LP-DDR3)Ball #VCCTS3_3 AB36RSVD AL22DCPRTC V15RSVD AK33VCCSATAPHY N45VCCSATAPHY T45RSVD CL14VCCCLK7 AJ26VCCCLK5 AL39VCCST AJ20VCCST_PWRGD

Signal Name(LP-DDR3)Ball #VSS AH20VSS AH21VSS AH22VSS AH23VSS AH25VSS AH26VSS AH27VSS AH28VSS AH29VSS AH30VSS AH31VSS AH32VSS AH33VSS AH34VSS AH44VSS

Signal Name(LP-DDR3)Ball #VSS BH39VSS BH41VSS BH43VSS BH7VSS BJ44VSS BK13VSS BK15VSS BK39VSS BK7VSS BL10VSS BL12VSS BL2VSS BL4VSS BL40VSS BL42VSS BL44

Signal Name(LP-DDR3)Ball #VSS CM19VSS CM21VSS CM23VSS CM25VSS CM31VSS CM35VSS CM43VSS CN1VSS CN26VSS CN42VSS CN5VSS CN8VSS CP17VSS CP29VSS CP3VSS CR14

Figure 1. Processor Platform Block Diagram Gigabit Network ConnectionUSB 2.0/3.0 PortsHD Audio CodecTPMDDR3L/LPDDR3 Digital Display Interface x 2BIOS/

Signal Name(LP-DDR3)Ball #VSS R6VSS R8VSS T13VSS T15VSS T19VSS T23VSS T29VSS U14VSS U20VSS U22VSS U24VSS U26VSS U28VSS U32VSS U34VSS V17VSS V2VSS V40V

U-Processor Ball Information (BGA1168)This section contains ball information for the 5th Generation Intel® Core™ processorfamily based on U-Processor

Signal Name(DDR3)Ball #DCPRTC AE7DCPSUS1 AD10DCPSUS1 AD8DCPSUS2 AH13DCPSUS3 J13DCPSUS4 AB8DCPSUSBYP AG19DCPSUSBYP AG20DDI1_TXN[0] C54DDI1_TXN[1] B58DD

Signal Name(DDR3)Ball #HDA_SDO /I2S0_TXDAU11HDA_SYNC /I2S0_SFRMAV11HSIOPC / GPIO71 Y2I2C0_SCL / GPIO5 F3I2C0_SDA / GPIO4 F2I2C1_SCL / GPIO7 F1I2C1_SDA

Signal Name(DDR3)Ball #RSVD V59RSVD U59RSVD AL1RSVD AP7RSVD AM11RSVD AV62RSVD D58RSVD P20RSVD R20RSVD N60RSVD AV2RSVD AF20RSVD AB21RSVD AY14RSVD AW14R

Signal Name(DDR3)Ball #SA_DQ44 AV54SA_DQ45 AU54SA_DQ3 AK62SA_DQ46 AV52SA_DQ47 AU52SB_DQ0 AY31SB_DQ1 AW31SB_DQ2 AY29SB_DQ3 AW29SB_DQ4 AV31SB_DQ5 AU31SB

Signal Name(DDR3)Ball #SATA1GP / GPIO35 U1SATA2GP / GPIO36 V6SATA3GP / GPIO37 AC1SATALED# U3SB_BA0 AL35SB_BA1 AM36SB_BA2 AU49SB_CAS# AM33SB_CK#0 AM38S

Signal Name(DDR3)Ball #SB_MA15 AP46SB_MA2 AP42SB_MA3 AR42SB_MA4 AR45SB_MA5 AP45SB_MA6 AW46SB_MA7 AY46SB_MA8 AY47SB_MA9 AU46SB_ODT0 AL32SB_RAS# AM35SB_

Signal Name(DDR3)Ball #USB3Tp2 A33USBRBIAS AJ11USBRBIAS# AJ10VCC F59VCC AB57VCC AD57VCC AG57VCC C24VCC C28VCC C32VCC C36VCC C40VCC C44VCC C48VCC C52VC

Signal Name(DDR3)Ball #VCCRTC AG10VCCSATA3PLL B11VCCSDIO U8VCCSDIO T9VCCSPI Y8VCCST AC22VCCST AE22VCCST AE23VCCST_PWRGD B59VCCSUS3_3 AH11VCCSUS3_3 AA9

• Intel® Device Protection Technology with Intel® Advanced Encryption StandardNew Instructions (Intel® AES-NI)• PCLMULQDQ Instruction• Intel® Device P

Signal Name(DDR3)Ball #VSS AJ43VSS AJ45VSS AJ47VSS AJ50VSS AJ52VSS AJ54VSS AJ56VSS AJ58VSS AJ60VSS AJ63VSS AK23VSS AK3VSS AK52VSS AL10VSS AL13VSS AL17

Signal Name(DDR3)Ball #VSS AU53VSS AU55VSS AU57VSS AU59VSS AV14VSS D62VSS AV16VSS AV20VSS AV24VSS AV28VSS AV33VSS AV34VSS AV36VSS AV39VSS AV41VSS AV43

Signal Name(DDR3)Ball #VSS F20VSS D5VSS F26VSS F30VSS F34VSS F38VSS G6VSS F46VSS F50VSS F54VSS F58VSS F61VSS G18VSS G22VSS G3VSS G5VSS G8VSS H13VSS H1

Table 57. U-Processor Ball Information (LP-DDR3, Non-Interleaved)Signal Name(LP-DDR3)Ball #ACPRESENT /GPIO31AJ8APWROK AB5BATLOW# / GPIO72 AN4BMBUSY# /

Signal Name(LP-DDR3)Ball #DDI1_TXN[3] A57DDI1_TXP[0] C55DDI1_TXP[1] C58DDI1_TXP[2] A55DDI1_TXP[3] B57DDI2_TXN[0] C51DDI2_TXN[1] C53DDI2_TXN[2] C49DDI2

Signal Name(LP-DDR3)Ball #JTAGX AE63LAD0 AU14LAD1 AW12LAD2 AY12LAD3 AW11LAN_PHY_PWR_CTRL/ GPIO12AM7LFRAME# AV12OC0# / GPIO40 AL3OC1# / GPIO41 AT1OC2#

Signal Name(LP-DDR3)Ball #RSVD AB21RSVD AY14RSVD AW14RSVD E15RSVD E13RSVD AL11RSVD AC4RSVD A5RSVD N23RSVD T23RSVD U10RSVD R23RSVD L11RSVD K10RSVD F22R

Signal Name(LP-DDR3)Ball #SB_DQ7 AU29SA_DQ4 AH61SB_DQ8 AY27SB_DQ9 AW27SB_DQ10 AY25SB_DQ11 AW25SB_DQ12 AV27SB_DQ13 AU27SB_DQ14 AV25SB_DQ15 AU25SB_DQ32

Signal Name(LP-DDR3)Ball #SB_CK1 AL38SB_CKE0 AY49SB_CKE1 AU50SB_CKE2 AW49SB_CKE3 AV50SB_CS#0 AM32SB_CS#1 AK32SA_DQ16 AP58SA_DQ17 AR58SA_DQ26 AM54SA_DQ

Signal Name(LP-DDR3)Ball #SB_CAB2 AK35SDIO_CLK / GPIO64 E3SDIO_CMD / GPIO65 F4SDIO_D0 / GPIO66 D3SDIO_D1 / GPIO67 E4SDIO_D2 / GPIO68 C3SDIO_D3 / GPIO6

• Memory Open and Closed Loop Throttling• Memory Thermal Throttling• External Thermal Sensor (TS-on-DIMM and TS-on-Board)• Render Thermal Throttling•

Signal Name(LP-DDR3)Ball #VCC C44VCC C48VCC C52VCC C56VCC E23VCC E25VCC E27VCC E29VCC E31VCC E33VCC E35VCC E37VCC E39VCC E41VCC E43VCC E45VCC E47VCC E

Signal Name(LP-DDR3)Ball #VCCSUS3_3 AE20VCCSUS3_3 AE21VCCTS1_5 J15VCCUSB3PLL B18VDDQ AH26VDDQ AJ31VDDQ AJ33VDDQ AJ37VDDQ AN33VDDQ AP43VDDQ AR48VDDQ AY

Signal Name(LP-DDR3)Ball #VSS AK52VSS AL10VSS AL13VSS AL17VSS AL20VSS AL22VSS AL23VSS AL26VSS AL29VSS AL31VSS AL33VSS AL36VSS AL39VSS AL40VSS AL45VSS

Signal Name(LP-DDR3)Ball #VSS AV36VSS AV39VSS AV41VSS AV43VSS AV46VSS AV49VSS AV51VSS AV55VSS AV59VSS AV8VSS AW16VSS AW24VSS AW33VSS AW35VSS AW37VSS A

Signal Name(LP-DDR3)Ball #VSS G18VSS G22VSS G3VSS G5VSS G8VSS H13VSS H17VSS H57VSS J10VSS J22VSS J59VSS J63VSS K1VSS K12VSS R22VSS L13VSS L15VSS L17VS

Term DescriptionDVI*Digital Visual Interface. DVI* is the interface specified by the DDWG (Digital DisplayWorking Group)EC Embedded ControllerECC Erro

Term DescriptionMLC Mid-Level CacheMSI Message Signaled InterruptMSL Moisture Sensitive LabelingMSR Model Specific RegistersNCTFNon-Critical to Functi

Term DescriptionTCONTROLTCONTROL is a static value that is below the TCC activation temperature and used as atrigger point for fan speed control. When

Document DocumentNumber /LocationDDR3 SDRAM Specification http://www.jedec.orgDisplayPort* Specification http://www.vesa.orgIntel® 64 and IA-32 Archit

2.0 InterfacesSystem Memory Interface• LPDDR3 down or DDR3L/DDR3L-RS Non-ECC Unbuffered Small Outline Dual In-Line Memory Modules with a maximum of o

Table 4. Supported DDR3L / DDR3L-RS SO-DIMM Module Configurations Per ChannelRawCardVersionSO-DIMMCapacitySDRAMOrganizationSDRAMDensity# ofSDRAMDevice

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described

Table 7. DRAM System Memory Timing SupportProcessor DRAMDeviceTransferRate(MT/s)tCL(tCK)tRCD(tCK)tRP(tCK)tCWL(tCK)CommandModeIntel® Core™ MProcessorDD

Out-of-Order SchedulingWhile leveraging the Just-in-Time Scheduling and Command Overlap enhancements,the system memory controller continuously monitor

Figure 2. Intel® Flex Memory Technology OperationsCH BCH AB BCBBCNon interleaved accessDual channel interleaved accessTOMCH A and CH B can be configur

• Next Generation Intel Clear Video Technology HD Support is a collection of videoplayback and enhancement features that improve the end user’s viewin

Vertex Fetch (VF) StageThe VF stage executes 3DPRIMITIVE commands. Some enhancements have beenincluded to better support legacy D3D APIs as well as SG

Logical 128-Bit Fixed BLT and 256 Fill EngineThis BLT engine accelerates the GUI of Microsoft Windows* operating systems. The128-bit BLT engine provid

• The processor supports streaming any 3 independent and simultaneous displaycombination of DisplayPort*/HDMI*/eDP*/ monitors. In the case of 3simulta

A DisplayPort* consists of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal.The Main Link is a unidirectional, high-bandwidth, and low lat

Figure 5. HDMI* OverviewHDMI SourceHDMI SinkTMDS Data Channel 0Hot-Plug DetectHDMI Tx HDMI RxTMDS Data Channel 1TMDS Data Channel 2TMDS Clock ChannelC

The processor will continue to support Silent stream. Silent stream is an integratedaudio feature that enables short audio streams, such as system eve

ContentsRevision History...91.0 Introdu

Table 10. Multiple Display Configuration for Intel® Core™ M Processor FamilyDisplay 1 Display 2 Display 3 MaximumResolutionDisplay 1MaximumResolutionD

Table 12. DisplayPort and embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – LinkData Rate of RBR, HBR, and HBR2 for Intel® Core™ M Processor Famil

Figure 6. PECI Host-Clients Connection ExampleVTTHost / OriginatorQ1nXQ21XPECICPECI<10pF/NodeQ3nXVTTPECI ClientAdditional PECI ClientsProcessor—Int

3.0 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in theprocessor.The implementation of the features m

• More reliable: Due to the hardware support, VMMs can now be smaller, lesscomplex, and more efficient. This improves reliability and availability and

• Descriptor-Table Exiting— Descriptor-table exiting allows a VMM to protect a guest operating systemfrom an internal (malicious software based) attac

Figure 7. Device to Domain Mapping StructuresRoot entry 0Root entry NRoot entry 255Context entry 0Context entry 255Context entry 0Context entry 255(Bu

• Memory controller and processor graphics comply with the Intel VT-d 1.2Specification• Two Intel VT-d DMA remap engines— iGFX DMA remap engine— Defau

Intel TXT is a set of extensions designed to provide a measured and controlled launchof system software that will then establish a protected environme

Intel® Turbo Boost Technology 2.0The Intel Turbo Boost Technology 2.0 allows the processor core to opportunisticallyand automatically run faster than

4.2.5 Package C-States...504.2.6 Package C-States and Display Resol

cryptographic applications, such as applications that perform bulk encryption/decryption, authentication, random number generation, and authenticated

• Provides extensions to scale processor addressability for both the logical andphysical destination modes• Adds new features to enhance performance o

Power Aware Interrupt Routing (PAIR)The processor includes enhanced power-performance technology that routesinterrupts to threads or cores based on th

Supervisor Mode Access Protection (SMAP)Supervisor Mode Access Protection provides the next level of system protection byblocking a malicious user fro

4.0 Power ManagementThis chapter provides information on the following power management topics:• Advanced Configuration and Power Interface (ACPI) St

Figure 9. Processor Package and Core C-StatesOne or more cores or GT executing instructionsAll cores and GT in C3 or deeper, L3 may be flushed and tur

State DescriptionC7Execution cores in this state behave similarly to the C6 state. If all execution coresrequest C7 state, L3 cache ways are flushed u

• Multiple frequency and voltage points for optimal performance and powerefficiency. These operating points are known as P-states.• Frequency selectio

While individual threads can request low-power C-states, power saving actions onlytake place once the core C-state is resolved. Core C-states are auto

Core C1/C1E StateC1/C1E is a low power state entered when all threads within a core execute a HLT orMWAIT(C1/C1E) instruction.A System Management Inte

7.5 Signal Groups...857.6 Test Access Port (TAP) C

This feature is disabled by default. BIOS must enable it in thePMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured bythis reg

Table 17. Coordination of Core Power States at the Package LevelPackage C-State Core 1C0 C1 C3 C6 C7 C8 C9 C10Core 0C0 C0 C0 C0 C0 C0 C0 C0 C0C1 C0 C1

• All cores are in a power state deeper than C1/C1E state; however, the packagelow-power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL M

Core break events are handled the same way as in package C3 or C6 state.Package C8 StateThe processor enters C8 states when the core with the highest

Table 18. Package C-States and Display ResolutionsPSR Number of Displays 1Native Resolution 2Deepest AvailablePackage C-StateDisabled Single3200x1800

Disabling Unused System Memory OutputsAny system memory (SM) interface signal that goes to a memory in which it is notconnected to any actual memory d

waking-up all page-buffers are empty.) The LPDDR does not have a DLL. As aresult, the power savings are as good as PPD/DLL-off, but will have lower ex

When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,the processor core flushes pending cycles and then enters SDRAM ranks

In C3 or deeper power state, the processor internally gates VDDQ for the majority ofthe logic to reduce idle power while keeping all critical DDR pins

performance. The processor core control is maintained by an embedded controller.The graphics driver dynamically adjusts between P-States to maintain o

Figures1 Processor Platform Block Diagram...112 Intel® Flex Memory Technolo

5.0 Thermal ManagementThe thermal solution provides both component-level and system-level thermalmanagement. To allow for the optimal operation and l

Intel® Turbo Boost Technology 2.0 Power MonitoringWhen operating in turbo mode, the processor monitors its own power and adjusts theturbo frequencies

Figure 12. Package Power ControlTurbo Time ParameterTurbo Time Parameter is a mathematical parameter (units in seconds) that controlsthe Intel Turbo B

Configurable TDPNote: Configurable TDP availability may vary between the different SKUs.With cTDP, the processor is now capable of altering the maxim

Off-lining core activity is the ability to dynamically scale a workload to a limited subsetof cores in conjunction with a lower turbo power limit. It

Table 21. Thermal Design Power (TDP) SpecificationsSegment andPackageProcessor IACores, GraphicsConfig. and TDPConfiguration CoreFrequencyGraphicsFreq

Table 23. Idle Power SpecificationSymbol Parameter Min Typical Max Unit NotePPACKAGE(C6)Package power in Package C6 state — — 0.6 W 1, 2PPACKAGE(C7)Pa

Thermal Control Circuit (TCC) Activation OffsetTCC Activation Offset can be used to activate the Adaptive Thermal Monitor attemperatures lower than Tj

times are independent of processor frequency. A small amount of hysteresis has beenincluded to prevent excessive clock modulation when the processor t

Digital Thermal Sensor Accuracy (Taccuracy)The DTS is expected to work within ±5° C over the operating range.Fan Speed Control with Digital Thermal Se

Tables1 Terminology... 132 Related Documents..

PROCHOT# only as a backup in case of system cooling failure. Overall, the systemthermal design should allow the power delivery circuitry to operate wi

Mode may be used in conjunction with the Adaptive Thermal Monitor. However, if thesystem software tries to enable On-Demand mode at the same time the

6.0 Signal DescriptionThis chapter describes the processor signals. The signals are arranged in functionalgroups according to the associated interfac

Signal Name Description Direction /Buffer TypeSA_RAS#, SB_RAS#RAS: These signals are used with CAS# and WE# to definethe command being entered.OSA_CAS

Memory Compensation and Miscellaneous SignalsTable 27. LPDDR3 / DDR3L / DDR3L-RS Reference and Compensation SignalsSignal Name Description Direction /

embedded DisplayPort* (eDP*) SignalsTable 29. embedded Display Port* SignalsSignal Name Description Direction / Buffer TypeeDP_TXP[3:0]eDP_TXN[3:0]emb

Signal Name Description Direction / BufferTypePROC_TDIProcessor Test Data In: This signal transfers serialtest data into the processor. This signal pr

Power Sequencing SignalsTable 33. Power Sequencing SignalsSignal Name Description Direction / BufferTypePROCPWRGDThe processor requires this input sig

Sense SignalsTable 35. Sense SignalsSignal Name Description Direction /Buffer TypeVCC_SENSEVSS_SENSEVCC_SENSE and VSS_SENSE provide an isolated, low-i

Processor Internal Pull-Up / Pull-Down TerminationsTable 37. Processor Internal Pull-Up / Pull-Down TerminationsSignal Name Pull Up / Pull Down Rail V

52 Package Mechanical Attributes...9653 Package Loading Specifications

7.0 Electrical SpecificationsThis chapter provides the processor electrical specifications including integratedvoltage regulator (VR), VCC Voltage Id

Table 38. Voltage Regulator (VR) 12.5 Voltage IdentificationBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC0 0 0 0 0 0 0 0 00h 0.00000 0 0 0 0 0 0 1 01h 0.500

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC0 1 0 0 0 0 1 0 42h 1.15000 1 0 0 0 0 1 1 43h 1.16000 1 0 0 0 1 0 0 44h 1.17000 1 0 0 0 1 0 1 45h 1.18000 1 0 0

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC1 0 0 0 0 1 1 0 86h 1.83001 0 0 0 0 1 1 1 87h 1.84001 0 0 0 1 0 0 0 88h 1.85001 0 0 0 1 0 0 1 89h 1.86001 0 0 0

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC1 1 0 0 1 0 1 0 CAh 2.51001 1 0 0 1 0 1 1 CBh 2.52001 1 0 0 1 1 0 0 CCh 2.53001 1 0 0 1 1 0 1 CDh 2.54001 1 0 0

Reserved or Unused SignalsThe following are the general types of reserved (RSVD) signals and connectionguidelines:• RSVD – these signals should not be

Signal Group Type SignalsSingle ended DDR3L/DDR3L-RS/LPDDR3 Bi-directionalSA_DQ[63:0], SB_DQ[63:0]Differential DDR3L/DDR3L-RS/LPDDR3 Bi-directionalSA_

Signal Group Type SignalsDigital Display InterfaceDifferential DDI Output DDIB_TXP[3:0], DDIB_TXN[3:0], DDIC_TXP[3:0],DDIC_TXN[3:0]]Notes: 1. See Sign

Symbol Parameter Segment Min Typ Max Unit Note1Voltage Range forProcessor Idle Mode(Package C7 Plus)All 1.3 — —Voltage Range forProcessor Idle Mode(Pa

Table 41. Memory Controller (VDDQ) Supply DC Voltage and Current SpecificationsSymbol Parameter Min Typ Max Unit NoteVDDQ (DDR3L/DDR3L-RS)Processor I/

Revision HistoryRevision Description Date001 • Initial Release September 2014002• Added Intel® Transactional Synchronization Extensions - NewInstructi

Symbol Parameter Min Typ Max Units Notes1RON_UP(CK)DDR3L/DDR3L-RS ClockBuffer pull-upResistance20 26 32 Ω5, 11,13RON_DN(CK)DDR3L/DDR3L-RS ClockBuffer

Symbol Parameter Min Typ Max Units Notes1SM_RCOMP1 Data COMP Resistance 118.8 120 121.2 Ω 8SM_RCOMP2 ODT COMP Resistance 99 100 101 Ω 8Notes: 1. Unles

Symbol Parameter Min Typ. Max Unit NoteRON_DN(CMD)LPDDR3 Command Bufferpull-down Resistance19 25 31 Ω 5, 12RON_UP(CTL)LPDDR3 Control Bufferpull-up Res

Table 45. Digital Display Interface Group DC SpecificationsSymbol Parameter Min Typ Max UnitsVILHPD Input Low Voltage — — 0.8 VVIHHPD Input High Volta

Symbol Parameter Min Max Units Notes1VIHInput High Voltage (PROC_TCK,PROC_TRST#)VccST * 0.7 — V 2, 4VHYSTERESISHysteresis Voltage VccST* 0.2 — V —RONB

Symbol Definition and Conditions Min Max Units Notes1VnNegative-Edge ThresholdVoltage0.275 * VccST0.525 * VccSTV —VpPositive-Edge ThresholdVoltage0.55

8.0 Package SpecificationsPackage Mechanical AttributesThe processors use a Flip Chip technology and Multi-Chip package (MCP) available in aBall Grid

Package Loading SpecificationsTable 53. Package Loading SpecificationsMaximum Static Normal Load Limit NotesU-Processor Line 67 N (15 lbf) 1, 2, 3Inte

9.0 Processor Ball and Signal InformationThis chapter provides the processor Ball information.Intel® Core™ M Processor Family Ball Information(BGA123

Signal Name(LP-DDR3)Ball #DDPB_CTRLCLK BP43DDPB_CTRLDATA BN42DDPC_CTRLCLK BP41DDPC_CTRLDATA BR40SM_PG_CNTL1 BL14SM_RCOMP0 CV7SM_RCOMP1 CP7SM_RCOMP2 CT