Intel AY80609007293AA Datový list

Document Number: 325310-001 Intel® Atom™ Processor Z6xx Series Datasheet For the Intel® Atom™ Processor Z670 on 45-nm Process Technology April

Introduction 10 Datasheet Document Location/ Comments Intel® 64 and IA-32 Architectures Software Developer's Manuals Volume 1: Basic A

Signal Descriptions Datasheet 11 2 Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups ac

Signal Descriptions 12 Datasheet Signal Direction Type Description SM_SREN# I CMOS1.8 Self-refresh enable: Signal from the chipset asserted aft

Signal Descriptions Datasheet 13 2.1.2 cDMI Interface Table 2-4. cDMI Interface Signal Signal Direction Type Description CDMI_RCOMP[1:0] I Anal

Signal Descriptions 14 Datasheet Signal Direction Type Description CDVO_STALL# I AGTL+ Stall: Allows PCH to throttle the sending of display dat

Signal Descriptions Datasheet 15 2.1.5 LGI/LGIe (Legacy) Signals Table 2-7. LGI/LGIe Legacy Signals Signal Direction Type Description VID[6:0]

Signal Descriptions 16 Datasheet Signal Direction Type Description PWRMODE[2:0] I CMOS Power mode: The chipset is expected to sequence Processo

Signal Descriptions Datasheet 17 2.1.7 Power Signals Table 2-9. Power Signals Signal Type Description VCC PWR Processor core supply voltag

Power Management 18 Datasheet 3 Power Management Processor supports fine grain power management by having several partitions of voltage island

Power Management Datasheet 19 Figure 3-1. Thread Low Power States C2†C0StopGrantCore statebreakP_LVL2 orMWAIT(C2)C1/MWAITCore statebreakMWAIT(C1

2 Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

Power Management 20 Datasheet 3.1.1 Cx State Definitions • C0 State—Full On This is the only state that runs software. All clocks are runnin

Power Management Datasheet 21 • C4E The C4E state is essentially the same as the C4 state except that the core processor will transition to the

Electrical Specifications 22 Datasheet 4 Electrical Specifications This chapter contains signal group descriptions, absolute maximum ratings,

Electrical Specifications Datasheet 23 4.4 Voltage Identification (VID) The VCC and VNN voltage inputs use two encoding pins (VIDEN[1:0]) to en

Electrical Specifications 24 Datasheet 4.4.2 VID Table Note: 1. Processor will not support the entire range of the voltages listed in the V

Electrical Specifications Datasheet 25 VID[6:0] VCC /VNN VID[6:0] VCC /VNN VID[6:0] VCC /VNN VID[6:0] VCC /VNN 1Ch 1.1500V 3Ch

Electrical Specifications 26 Datasheet Symbol Parameter Minimum Maximum Unit Note VCCD180 1.8-V LVDS I/O supply voltage -0.3 1.9 V V

Electrical Specifications Datasheet 27 Symbol Parameter Min. Typ. Max. Unit Notes1,2 VCCPAOAC VCCPAOAC supply voltage 0.9975 1.05 1.10

Electrical Specifications 28 Datasheet 8. This is the sum of current on both rails. 9. Specification based on LVDS panel configuration of 102

Electrical Specifications Datasheet 29 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Datasheet 3 Contents 1 Introduction ... 6 1.1

Electrical Specifications 30 Datasheet Symbol Parameter Min. Typ. Max. Unit Notes ∆VOD Change in differential output voltage − − 50

Thermal Specifications and Design Considerations Datasheet 31 5 Thermal Specifications and Design Considerations The processor requires a therm

Thermal Specifications and Design Considerations 32 Datasheet 3. Scenario Power examines a common use case and may be more indicative of a mor

Thermal Specifications and Design Considerations Datasheet 33 When the TM1 mode is enabled and a high temperature situation exists, the clocks w

Thermal Specifications and Design Considerations 34 Datasheet An external signal, PROCHOT# (processor hot) is asserted when the processor detec

Thermal Specifications and Design Considerations Datasheet 35 Unlike traditional thermal devices, the DTS outputs a temperature relative to the

Thermal Specifications and Design Considerations 36 Datasheet PROCHOT#. Refer to the Intel® 64 and IA-32 Architectures Software Developer'

Package Mechanical Specifications and Pin Information Datasheet 37 6 Package Mechanical Specifications and Pin Information This chapter describ

Package Mechanical Specifications and Pin Information 38 Datasheet Figure 6-1. Package Mechanical Drawing

Package Mechanical Specifications and Pin Information Datasheet 39 6.2 Processor Pinout Assignment Table 6-1, Table 6-2 and Table 6-3 are graph

4 Datasheet 6 Package Mechanical Specifications and Pin Information ... 37 6.1 Package Mechanical Specifications

Package Mechanical Specifications and Pin Information 40 Datasheet Table 6-1. Processor Pinout (Top View—Columns 21–31) 31 30 29 28 27 2

Package Mechanical Specifications and Pin Information Datasheet 41 Table 6-2. Processor Pinout (Top View—Columns 11–20) 20 19 18 17 16 15

Package Mechanical Specifications and Pin Information 42 Datasheet Table 6-3. Processor Pinout (Top View—Columns 1–10) 10 9 8 7 6 5 4 3

Package Mechanical Specifications and Pin Information Datasheet 43 Table 6-4. Pinout—Ordered by Signal Name Pin Name Pin # BCLK_P M2 BCLK_N N

Package Mechanical Specifications and Pin Information 44 Datasheet Pin Name Pin # SM_DQ11 A29 SM_DQ12 B25 SM_DQ13 A24 SM_DQ14 B24 SM_DQ15

Package Mechanical Specifications and Pin Information Datasheet 45 Pin Name Pin # VCC W12 VCC W14 VCC W16 VCC W18 VCC W2 VCC W20 VCC W22

Package Mechanical Specifications and Pin Information 46 Datasheet Pin Name Pin # VNN P30 VNN R10 VNN R12 VNN R14 VNN R16 VNN R18 VNN R

Package Mechanical Specifications and Pin Information Datasheet 47 Pin Name Pin # VSS D3 VSS E12 VSS E14 VSS E18 VSS E20 VSS E24 VSS E26

Datasheet 5 Revision History Document Number Revision Number Description Revision Date 325314 001 • Initial release. April 2011 §

Introduction 6 Datasheet 1 Introduction The datasheet describes the architecture, features, buffers, signal descriptions, power management, pi

Introduction Datasheet 7 1.2 Interfaces 1.2.1 System Memory Support • One channel of DDR2 memory • 32-bit data bus • Memory DDR2 transfer r

Introduction 8 Datasheet 1.2.4 cDVO • Peak raw BW of 800MT/s • Supports low power management schemes • Supports AGTL+ interface 1.2.5 LVDS

Introduction Datasheet 9 Acronym Description LVDS Low Voltage Differential Signaling, a high speed, low power data transmission standard used