Intel AY80609007293AA Datový list stáhnout pdf (Strana 14)

Signal Descriptions

14 Datasheet

Signal

Direction

Type

Description

CDVO_STALL#

AGTL+

Stall: Allows PCH to throttle the sending of display data.

CDVO_TXDPWR#

AGTL+

Line wakeup for output: When asserted, the PCH will

power-up its receivers on CDVO_TX[5:0] and

CDVO_TXSTB_ODD#.

CDVO_TXSTB_ODD#,

CDVO_TXSTB_EVEN#

AGTL+

Data strobe output: Strobes for CDVO_TX[5:0].

CDVO_VBLANK#

AGTL+

Vertical blank: Indication from PCH indicating the start of

the vertical blank period.

CDVO_GVREF

Analog

Strobe signals' reference voltage for CDVO: Externally

set by means of a passive voltage divider. Voltage should

be 2/3 V

CCP

when configured for GTL.

CDVO_CVREF

Analog

Non-Strobe Signals' Reference Voltage for CDVO:

Externally set by means of a passive voltage divider.

Voltage should be 2/3 V

CCP

when configured for GTL.

2.1.4 LVDS Display Port Interface

Table 2-6. LVDS Display Port Interface Signals

Signal

Direction

Type

Description

LA_DATAN[3:0]

LVDS

Differential Data Output (Negative)

LA_DATAP[3:0]

LVDS

Differential Data Output (Positive)

LA_CLKN

LVDS

Differential Clock Output (Negative)

LA_CLKP

LVDS

Differential Clock Output (Positive)

LA_IBG

Analog

External Voltage Ref BG: Connected to high-precision

resistor on motherboard to VSS.

LA_VBG

Analog

External Voltage Ref BG: Requires external 1.25 V ±2%

supply.

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