Intel A2Y15AV Datový list Strana 262
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- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Processor Configuration Registers
262 Datasheet, Volume 2
2.18.2 CAP_REG—Capability Register
This register reports general remapping hardware capabilities.
B/D/F/Type: 0/0/0/GFXVTBAR
Address Offset: 8–Fh
Reset Value: 00C0000020E60262h
Access: RO
Size: 64 bits
BIOS Optimal Default 000h
Bit Access
Reset
Value
RST/
PWR
Description
63:56 RO 0h Reserved (RSVD)
55 RO 1b Uncore
DMA Read Draining (DRD)
0 = Hardware does not support draining of DMA read requests.
1 = Hardware supports draining of DMA read requests.
54 RO 1b Uncore
DMA Write Draining (DWD)
0 = Hardware does not support draining of DMA write requests.
1 = Hardware supports draining of DMA write requests.
53:48 RO 000000b Uncore
Maximum Address Mask Value (MAMV)
The value in this field indicates the maximum supported value for
the Address Mask (AM) field in the Invalidation Address register
(IVA_REG) and IOTLB Invalidation Descriptor (iotlb_inv_dsc).
This field is valid only when the PSI field in Capability register is
reported as set.
47:40 RO
00000000
b
Uncore
Number of Fault-recording Registers (NFR)
Number of fault recording registers is computed as N+1, where N
is the value reported in this field.
Implementations must support at least one fault recording
register (NFR = 0) for each remapping hardware unit in the
platform.
The maximum number of fault recording registers per remapping
hardware unit is 256.
39 RO 0b Uncore
Page Selective Invalidation (PSI)
0 = Hardware supports only domain and global invalidates for
IOTLB
1 = Hardware supports page selective, domain and global
invalidates for IOTLB.
Hardware implementations reporting this field as set are
recommended to support a Maximum Address Mask Value
(MAMV) value of at least 9.
38:38 RO 0h Reserved (RSVD)
37:34 RO 0000b Uncore
Super-Page Support (SPS)
This field indicates the super page sizes supported by hardware.
A value of 1 in any of these bits indicates the corresponding
super-page size is supported. The super-page sizes
corresponding to various bit positions within this field are:
0 = 21-bit offset to page frame (2 MB)
1 = 30-bit offset to page frame (1 GB)
2 = 39-bit offset to page frame (512 GB)
3 = 48-bit offset to page frame (1 TB)
Hardware implementations supporting a specific super-page size
must support all smaller super-page sizes; that is, only valid
values for this field are 0001b, 0011b, 0111b, 1111b.
- Mobile 3rd Generation Intel 1
- Processor Family 1
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Revision History 11
- 12 Datasheet, Volume 2 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 PCI Devices and Functions 16
- 2.3 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.3.1 Legacy Address Range 19
- 20 Datasheet, Volume 2 20
- 2.3.1.3 PAM (C_0000h–F_FFFFh) 21
- 22 Datasheet, Volume 2 22
- 2.3.2.2 TSEG 23
- 2.3.2.5 Pre-allocated Memory 24
- 2.3.2.7 Intel 25
- Management Engine (Intel 25
- ME) UMA 25
- 26 Datasheet, Volume 2 26
- 2.3.3.4 High BIOS Area 27
- 28 Datasheet, Volume 2 28
- Datasheet, Volume 2 29 29
- 2.3.4.5 Programming Model 30
- Host/System View 31
- Physical Memory 31
- (DRAM Controller View) 31
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- Datasheet, Volume 2 35 35
- 36 Datasheet, Volume 2 36
- 2.3.11 I/O Address Space 38
- 2.3.12 MCTP and KVM Flows 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.4 I/O Mapped Registers 46
- 2.5.6 CC—Class Code Register 52
- DMA protected range register 59
- 2.5.19 MESEG_BASE—Intel 63
- 2.5.20 MESEG_MASK—Intel 64
- B4h bits 31:20) 80
- 2.6.6 CC—Class Code Register 92
- Register 100
- Port Command Register 112
- 11:10 RW-O 11b Uncore 115
- 5RW-V 0b Uncore 117
- Registers 132
- 104–107h 133
- 108–10Bh 133
- 10C–10Dh 134
- 110–113h 135
- 23 RO 0h Reserved (RSVD) 135
- 114–117h 136
- 11A–11Bh 137
- DA0–DA3h 138
- DA4–DA7h 139
- DA8–DABh 140
- DAC–DAFh 141
- DB0–DB3h 142
- DB4–DB7h 143
- DB8–DBBh 144
- DBC–DBFh 145
- DD8–DDBh 146
- Registers 148
- PCI device 149
- 2.8.6 CC—Class Code Register 152
- Mapped Range Address Register 154
- 2.9 Device 2 IO Registers 160
- 2.10 PCI Device 6 Registers 161
- 2.10.6 CC—Class Code Register 168
- 2RW 0bUncore 180
- of the table in DQWORDS (16 204
- 140–143h 208
- 144–147h 209
- 150–153h 210
- 158–15Bh 210
- 15C–15Fh 211
- 240–243h 211
- 244–247h 212
- C34–C37h 212
- D0C–D0Fh 213
- D34–D37h 213
- D6C–D6Fh 214
- DC0–DC3h 215
- DC4–DC7h 215
- : DCC–DCFh 216
- (DMIBAR) 217
- Declaration Capability 229
- 0 Registers 239
- 4000–4003h 240
- 4028–402Bh 242
- 42A4–42A7h 242
- 4294–4297h 244
- 4298–429Bh 244
- Channel 1 245
- 4404–4407h 247
- 4428–442Bh 247
- 4694–4697h 249
- 4698–469Bh 250
- 46A4–46A7h 250
- 740C–740Fh 251
- 7410–7413h 252
- 5004–5007h 254
- 5008–500Bh 255
- 5060–5063h 256
- Group Registers 257
- 4CB0–4CB3h 258
- 100–107h 290
- 108–10Fh 291
- 200–207h 293
- 208–20Fh 294
- FF0–FF3h 295
- 2.19 PCU MCHBAR Registers 296
- 5880–5883h 297
- 5888–588Bh 298
- Status Report Register 299
- Interrupt Register 300
- 5948–594Bh 301
- 5994–5997h 301
- 5998–599Bh 302
- 5C20–5C23h 302
- 5C24-5C27h 304
- 5D10–5D17h 306
- 2.20 PXPEPBAR Registers 308
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