Intel 8086-1 Uživatelský manuál

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September 1990 Order Number: 231455-005
8086
16-BIT HMOS MICROPROCESSOR
8086/8086-2/8086-1
Y
Direct Addressing Capability 1 MByte
of Memory
Y
Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages
Y
14 Word, by 16-Bit Register Set with
Symmetrical Operations
Y
24 Operand Addressing Modes
Y
Bit, Byte, Word, and Block Operations
Y
8 and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal
Including Multiply and Divide
Y
Range of Clock Rates:
5 MHz for 8086,
8 MHz for 8086-2,
10 MHz for 8086-1
Y
MULTIBUS System Compatible
Interface
Y
Available in EXPRESS
Ð Standard Temperature Range
Ð Extended Temperature Range
Y
Available in 40-Lead Cerdip and Plastic
Package
(See Packaging Spec. Order
Ý
231369)
The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is
implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin
CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations
to achieve high performance levels.
2314551
Figure 1. 8086 CPU Block Diagram
2314552
40 Lead
Figure 2. 8086 Pin
Configuration
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Strany 1 - 8086/8086-2/8086-1

September 1990 Order Number: 231455-005808616-BIT HMOS MICROPROCESSOR8086/8086-2/8086-1YDirect Addressing Capability 1 MByteof MemoryYArchitecture Des

Strany 2

8086Status bits S3through S7are multiplexed with high-order address bits and the BHEsignal, and aretherefore valid during T2through T4.S3and S4indi-ca

Strany 3

8086MASKABLE INTERRUPT (INTR)The 8086 provides a single interrupt request input(INTR) which can be masked internally by softwarewith the resetting of

Strany 4

8086EXTERNAL SYNCHRONIZATION VIA TESTAs an alternative to the interrupts and general I/Ocapabilities, the 8086 provides a single software-testable inp

Strany 5 - ). Only the pin

8086lines D7–D0as supplied by the inerrupt system logic(i.e., 8259A Priority Interrupt Controller). This byteidentifies the source (type) of the inter

Strany 6 - General Operation

8086ABSOLUTE MAXIMUM RATINGS*Ambient Temperature Under Bias ÀÀÀÀÀÀ0§Cto70§CStorage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa150§CVoltage on Any Pin withRespect t

Strany 7 - MINIMUM AND MAXIMUM MODES

8086A.C. CHARACTERISTICS (8086: TAe0§Cto70§C, VCCe5Vg10%)(8086-1: TAe0§Cto70§C, VCCe5Vg5%)(8086-2: TAe0§Cto70§C, VCCe5Vg5%)MINIMUM COMPLEXITY SYSTEM T

Strany 8 - 231455–6

8086A.C. CHARACTERISTICS (Continued)TIMING RESPONSESSymbol Parameter8086 8086-1 8086-2UnitsTestMin Max Min Max Min MaxConditionsTCLAV Address Valid De

Strany 9 - 231455–8

8086A.C. TESTING INPUT, OUTPUT WAVEFORM231455-11A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45Vfor a Logic ‘‘0’’. Timing measureme

Strany 10 - External Interface

8086WAVEFORMS (Continued)MINIMUM MODE (Continued)231455–14SOFTWARE HALTÐRD, WR, INTAeVOHDT/ReINDETERMINATENOTES:1. All signals switch between VOHand V

Strany 11 - 231455–9

8086A.C. CHARACTERISTICSMAX MODE SYSTEM (USING 8288 BUS CONTROLLER)TIMING REQUIREMENTSSymbol Parameter8086 8086-1 8086-2UnitsTestMin Max Min Max Min M

Strany 12 - Basic System Timing

8086Table 1. Pin DescriptionThe following pin function descriptions are for 8086 systems in either minimum or maximum mode. The ‘‘LocalBus’’ in these

Strany 13

8086A.C. CHARACTERISTICS (Continued)TIMING RESPONSESSymbol Parameter8086 8086-1 8086-2UnitsTestMin Max Min Max Min MaxConditionsTCLML Command Active 1

Strany 14 - D.C. CHARACTERISTICS (8086: T

8086A.C. CHARACTERISTICS (Continued)TIMING RESPONSES (Continued)Symbol Parameter8086 8086-1 8086-2UnitsTestMin Max Min Max Min MaxConditionsTRHAV RD I

Strany 15 - A.C. CHARACTERISTICS (8086: T

8086WAVEFORMSMAXIMUM MODE231455–1522

Strany 16 - (Continued)

8086WAVEFORMS (Continued)MAXIMUM MODE (Continued)231455–16NOTES:1. All signals switch between VOHand VOLunless otherwise specified.2. RDY is sampled n

Strany 17 - WAVEFORMS

8086WAVEFORMS (Continued)ASYNCHRONOUS SIGNAL RECOGNITION231455–17NOTE:1. Setup requirements for asynchronous signals only to guarantee recognition at

Strany 18 - WAVEFORMS (Continued)

8086WAVEFORMS (Continued)HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)231455–2125

Strany 19 - A.C. CHARACTERISTICS

8086Table 2. Instruction Set SummaryMnemonic andInstruction CodeDescriptionDATA TRANSFERMOVeMove: 76543210 76543210 76543210 76543210Register/Memory t

Strany 20

8086Table 2. Instruction Set Summary (Continued)Mnemonic andInstruction CodeDescriptionARITHMETIC 76543210 76543210 76543210 76543210ADDeAdd:Reg./Memo

Strany 21

8086Table 2. Instruction Set Summary (Continued)Mnemonic andInstruction CodeDescriptionLOGIC 76543210 76543210 76543210 76543210NOTeInvert 1111011w mo

Strany 22

8086Table 2. Instruction Set Summary (Continued)Mnemonic andInstruction CodeDescriptionJMPeUnconditional Jump: 76543210 76543210 76543210Direct within

Strany 23

8086Table 1. Pin Description (Continued)Symbol Pin No. Type Name and FunctionREADY 22 I READY: is the acknowledgement from the addressed memory or I/O

Strany 24

8086Table 2. Instruction Set Summary (Continued)Mnemonic andInstruction CodeDescription76543210 76543210PROCESSOR CONTROLCLCeClear Carry 11111000CMCeC

Strany 25

8086Table 1. Pin Description (Continued)Symbol Pin No. Type Name and FunctionS2,S1,S026– 28 O These signals float to 3-state OFF in ‘‘hold acknowledge

Strany 26 - Intel, 1978

8086Table 1. Pin Description (Continued)Symbol Pin No. Type Name and FunctionQS1,QS024, 25 O QUEUE STATUS: The queue status is valid during the CLK cy

Strany 27

8086FUNCTIONAL DESCRIPTIONGeneral OperationThe internal functions of the 8086 processor arepartitioned logically into two processing units. Thefirst i

Strany 28 - offset-high

8086231455–3Figure 3a. Memory OrganizationIn referencing word data the BIU requires one or twomemory cycles depending on whether or not thestarting by

Strany 29

8086231455–5Figure 4a. Minimum Mode 8086 Typical Configuration231455–6Figure 4b. Maximum Mode 8086 Typical Configuration8

Strany 30 - DATA SHEET REVISION REVIEW

8086can occur between 8086 bus cycles. These are re-ferred to as ‘‘Idle’’ states (Ti) or inactive CLK cycles.The processor uses these cycles for inter

Příbuzné modely 8086 | 8086-2 |

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