Intel 8XC251SA Uživatelský manuál stáhnout pdf

PRELIMINARY

8XC251SA/SB/SP/SQ

HIGH-PERFORMANCE

CHMOS MICROCONTROLLER

Commercial/Express

A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code

compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51

microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and

efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is

available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.

A variety of features can be selected by new user-programmable configurations.

■ Real-time and Programmed Wait State

Bus Operation

■ Binary-code Compatible with MCS

■ Pin Compatible with 44-pin PLCC and 40-

pin PDIP MCS 51 Sockets

■ Register-based MCS

251 Architecture

— 40-byte Register File

— Registers Accessible as Bytes, Words,

or Double Words

■ Enriched MCS 51 Instruction Set

— 16-bit and 32-bit Arithmetic and Logic

Instructions

— Compare and Conditional Jump

Instructions

— Expanded Set of Move Instructions

■ Linear Addressing

■ 256-Kbyte Expanded External Code/Data

Memory Space

■ ROM/OTPROM/EPROM Options:

16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or

without ROM/OTPROM/EPROM

■ 16-bit Internal Code Fetch

■ 64-Kbyte Extended Stack Space

■ On-chip Data RAM Options:

1-Kbyte (SA/SB) or 512-Byte (SP/SQ)

■ 8-bit, 2-clock External Code Fetch in

Page Mode

■ Fast MCS 251 Instruction Pipeline

■ User-selectable Configurations:

— External Wait States (0-3 wait states)

— Address Range & Memory Mapping

— Page Mode

■ 32 Programmable I/O Lines

■ Seven Maskable Interrupt Sources

with Four Programmable Priority

Levels

■ Three Flexible 16-bit Timer/counters

■ Hardware Watchdog Timer

■ Programmable Counter Array

— High-speed Output

— Compare/Capture Operation

— Pulse Width Modulator

— Watchdog Timer

■ Programmable Serial I/O Port

— Framing Error Detection

— Automatic Address Recognition

■ High-performance CHMOS Technology

■ Static Standby to 16-MHz Operation

■ Complete System Development

Support

— Compatible with Existing Tools

— New MCS 251 Tools Available:

Compiler, Assembler, Debugger, ICE

■ Package Options (PDIP, PLCC, and

Ceramic DIP)

1 2 3 4 5 6 ... 35 36

Shrnutí obsahu

Strany 1 - CHMOS MICROCONTROLLER

Strany 2

10 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER3.0 SIGNALSTable 6. Signal Descriptions Signal NameType DescriptionAlternate F

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PRELIMINARY 118XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERP3.0P3.1P3.3:2P3.5:4P3.6P3.7I/O Port 3. This is an 8-bit, bidirectional I/O port

Strany 4

12 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERVPPI Programming Supply Voltage. The programming supply voltage is applied to th

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PRELIMINARY 138XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 7. Memory Signal Selections (RD1:0)RD1:0P1.7/CEX/A17/WCLKP3.7/RD#/A16 P

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14 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER4.0 ADDRESS MAPTable 8. 8XC251SA/SB/SP/SQ Address MapInternal Address)Descriptio

Strany 7 - PRELIMINARY 7

PRELIMINARY 158XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER5.0 ELECTRICAL CHARACTERISTICSABSOLUTE MAXIMUM RATINGSStorage Temperature ...

Strany 8

16 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER5.1 D.C. CharacteristicsParameter values apply to all devices unless otherwise i

Strany 9 - PRELIMINARY 9

PRELIMINARY 178XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERVOH1Output High Voltage (Port 0 in External Address)VCC – 0.3VCC – 0.7VCC – 1.5V

Strany 10 - PRELIMINARY

18 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 5. IPD Test Condition, Powerdown Mode, VCC = 2.0 – 5.5VFigure 6. ICC vs.

Strany 11 - PRELIMINARY 11

PRELIMINARY 198XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER5.2 Definition of AC Symbols 5.3 A.C. CharacteristicsTest Conditions: Capa

Strany 12

Information in this document is provided in connection with Intel products. No license, express or implied, byestoppel or otherwise, to any intellect

Strany 13 - PRELIMINARY 13

20 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERTRLRH (2) RD# or PSEN# Pulse Width@ 12 MHz@ 16 MHz146.61052(1+N)TOSC – 20ns(4)T

Strany 14

PRELIMINARY 218XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERTAVDV1Address (P0) Valid to Valid Data/Instruction In@ 12 MHz@ 16 MHz243.21604(1

Strany 15 - PRELIMINARY 15

22 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER5.3.1 EXTERNAL BUS CYCLES, NONPAGE MODEFigure 7. External Bus Cycle: Code Fetch

Strany 16

PRELIMINARY 238XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 8. External Bus Cycle: Data Read (Nonpage Mode) XTAL1ALETLHLL†A7:0D7:0RD#

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24 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 9. External Bus Cycle: Data Write (Nonpage Mode) WR#P0P2/A16/A17TLHLL†TWL

Strany 18

PRELIMINARY 258XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER5.3.2 EXTERNAL BUS CYCLES, PAGE MODEFigure 10. External Bus Cycle: Code Fetch (P

Strany 19 - PRELIMINARY 19

26 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 11. External Bus Cycle: Data Read (Page Mode) XTAL1ALETLHLL†TRHDZ2RD#/PSE

Strany 20

PRELIMINARY 278XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 12. External Bus Cycle: Data Write (Page Mode) WR#P2P0/A16/A17TLHLL†TWLWH

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28 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER5.3.3 DEFINITION OF REAL-TIME WAIT SYMBOLS 5.3.4 EXTERNAL BUS CYCLES, REAL

Strany 22

PRELIMINARY 298XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 14. External Bus Cycle: Data Write (Nonpage Mode) Figure 15. External Bus

Strany 23 - PRELIMINARY 23

PRELIMINARY 38XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Figure 1. 8XC251SA/SB/SP/SQ Block Diagram SRC2 (8)Code Address (24)Clock &

Strany 24

30 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 16. External Bus Cycle: Data Write (Page Mode) Table 13. Real-time Wait A

Strany 25 - PRELIMINARY 25

PRELIMINARY 318XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER5.4 AC Characteristics — Serial Port, Shift Register ModeFigure 17. Serial Port

Strany 26 - A4212-03

32 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 18. External Clock Drive Waveforms Figure 19. AC Testing Input, Output Wa

Strany 27 - PRELIMINARY 27

33 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER6.0 THERMAL CHARACTERISTICSAll thermal impedance data is approximate for statica

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34 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER7.2 Programming and Verification Timing for Nonvolatile Memory Figure 21. Timing

Strany 29 - PRELIMINARY 29

PRELIMINARY 358XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERTAVQVAddress to Data Valid 48TOSCTELQVENABLE Low to Data Valid 48TOSCTEHQZData F

Strany 30

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4 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER1.0 NOMENCLATUREFigure 2. The 8XC251SA/SB/SP/SQ Family NomenclatureTable 1. Desc

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PRELIMINARY 58XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERTable 2 lists the proliferation options. See Figure 2 for the 8XC251SA/SB/SP/SQ f

Strany 33 - Handbook

6 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER2.0 PINOUTFigure 3. 8XC251SA/SB/SP/SQ 44-pin PLCC PackageAD4 / P0.4AD5 / P0.5AD

Strany 34

PRELIMINARY 78XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERFigure 4. 8XC251SA/SB/SP/SQ 40-pin PDIP and Ceramic DIP Packages123456789

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8 PRELIMINARY8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERTable 4. 8XC251SA/SB/SP/SQ Pin AssignmentPLCC DIP Name PLCC DIP Name1VSS123 VS

Strany 36

PRELIMINARY 98XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLERTable 5. 8XC251SA/SB/SP/SQ PLCC/DIP Pin Assignments Arranged by Functional Catego

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