Intel CM8063601537106 Datový list Strana 116
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Processor Uncore Configuration Registers
116 Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.2.8 SPAREINTERVAL
Defines the interval between normal and sparing operations. Interval is defined in dclk.
13.2.2.9 RASENABLES
RAS Enables Register
13.2.2.10 SMISPARECTL
Scalable Memory Interconnect Spare control register.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xa8
Bit Attr Default Description
31:29 RV - Reserved.
28:16 RW 0x320
NUMSPARE (numspare):
Sparing operation duration. System requests will be blocked during this interval
and only sparing copy operations will be serviced.
15:0 RW 0xc80
NORMAL OPERATION DURATION (normopdur):
Normal operation duration. System requests will be serviced during this
interval.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xac
Bit Attr Default Description
31:1 RV - Reserved.
0:0 RW_LB 0x0
MIRROREN (mirroren):
Mirror mode enable. The channel mapping must be set up before this bit will
have an effect on iMC operation. This changes the error policy.
Type: CFG PortID: N/A
Bus: 1 Device: 15 Function: 1
Bus: 1 Device: 29 Function: 1
Offset: 0xb4
Bit Attr Default Description
31:18 RV - Reserved.
17:17 RW 0x0
INTRPT_SEL_PIN (intrpt_sel_pin):
Enable pin signaling. When set the interrupt is signaled via the ERROR_N[0] pin
to get the attention of a BMC.
16:16 RW 0x0
INTRPT_SEL_CMCI (intrpt_sel_cmci):
(CMCI used as a proxy for NMI signaling). Set to enable CMCI (NMI) signaling.
Clear to disable CMCI (NMI) signaling. If both CMCI (NMI) and SMI enable bits
are set then only SMI is sent
- Processor E7 v2 1
- Contents 3
- Revision History 15
- 1 Overview 17
- 1.2 Terminology 18
- 1.3 Related Documents 21
- 1.4 State of Data 22
- The Processor Architecture 23
- Overview 23
- 2.2 Uncore Features 25
- 2.2.5 Home Agent (HA) 26
- 2.2.9 Config Agent (Ubox) 28
- 3 Cbo Functional Description 29
- 3.2.2.1 Core Address Decoders 30
- 3.2.3 SAD Address Spaces 31
- 3.2.4.1 DRAM Decoders 32
- 3.2.4.2 MMIO Decoders 32
- 3.2.8 NO_EGO Range 33
- 3.2.9 I/O Address Space 33
- 3.2.10 SAD Glossary 33
- 3.3 Viral Support 34
- 4 Home Agent Functional 35
- 4.2 Directory Support 36
- 4.3 RTID Allocation 36
- 4.4 Backup Tracker (BT) 36
- 4.5 NodeID Conventions 36
- 4.6 iMC Interface 37
- 38 Intel 38
- 5 iMC Functional Description 39
- 5.2 Operation 40
- 5.3 Memory Address Decode 41
- 5.3.3 Refresh 42
- 5.3.3.1 Refresh Priorities 43
- 44 Intel 44
- IIO Functional Description 45
- 46 Intel 46
- 6.2 PECI and JTAG 47
- 6.3.3.1 Port Bifurcation 48
- 6.3.3.2 Lane Reversal 48
- 6.4 Power Management 49
- 50 Intel 50
- 7 Reliability, Availability 51
- 7.1.1.1 Soft Errors 52
- 7.1.3 RASM Feature Summary 53
- 7.3.1.1 Feature Description 54
- 7.4 Memory RAS 55
- 7.4.4.2 Rank Sparing 56
- 7.4.9.1 Error Severity 56
- 7.5 IIO RAS 57
- 7.5.3 PCI Express RAS 58
- 7.6 System Level RAS Features 59
- 60 Intel 60
- 8 Reset Flow 61
- Reset Flow 62
- 62 Intel 62
- 9 Ubox Functional Description 63
- 9.4.2 TAP Access 64
- 10 PCU Functional Description 65
- PCU Functional Description 66
- 66 Intel 66
- 10.2.1.1 Thermal Management 67
- 10.6.2.1 Motivation 68
- 11 Performance Monitoring 69
- Performance Monitoring 70
- 70 Intel 70
- 12 Registers Overview and 71
- 72 Intel 72
- 12.2.1.1 PCI Bus Number 74
- 12.2.1.2 Uncore Bus Number 74
- 12.2.1.3 Device Mapping 74
- 12.2.1.5 Device Hiding 77
- 12.2.1.6 CSR Access Via PECI 78
- 12.3 Register Terminology 79
- 12.4 Notational Conventions 81
- 82 Intel 82
- Registers 83
- 13.1.2 DID 84
- 13.1.3 PCICMD 84
- 13.1.4 PCISTS 85
- 13.1.5 RID 86
- 13.1.6 CCR 86
- 13.1.7 CLSR 86
- 13.1.8 PLAT 87
- 13.1.9 HDR 87
- 13.1.10 BIST 87
- 13.1.11 SVID 87
- 13.1.12 SDID 88
- 13.1.13 CAPPTR 88
- 13.1.14 INTL 88
- 13.1.15 INTPIN 88
- 13.2.1.1 PXPCAP 91
- 13.2.1.2 MCMTR 92
- 13.2.1.3 TADWAYNESS_[0:11] 93
- 13.2.1.4 MCMTR2 95
- 13.2.1.5 MC_INIT_STATE_G 95
- 13.2.1.6 RCOMP_TIMER 96
- 13.2.1.7 PXPENHCAP 97
- 13.2.1.8 MH_MAINCNTL 97
- 13.2.1.9 MH_SENSE_500NS_CFG 98
- 13.2.1.11 MH_IO_500NS_CNTR 99
- 13.2.1.12 MH_CHN_ASTN 100
- 13.2.1.13 MH_TEMP_STAT 101
- 13.2.1.14 MH_EXT_STAT 103
- 13.2.1.15 SMB_STAT_[0:1] 103
- 0x180, 0x190 104
- 13.2.1.16 SMBCMD_[0:1] 105
- 13.2.1.17 SMBCNTL_[0:1] 106
- 0x188, 0x198 107
- 0x18c, 0x19c 108
- 13.2.1.19 SMB_PERIOD_CFG 109
- 13.2.1.20 SMB_PERIOD_CNTR 109
- 13.2.1.21 SMB_TSOD_POLL_RATE 109
- 13.2.2.1 PXPCAP 110
- 13.2.2.2 SPAREADDRESSLO 111
- 13.2.2.3 SPARECTL 112
- 13.2.2.4 SSRSTATUS 113
- 13.2.2.5 SCRUBADDRESSLO 114
- 13.2.2.6 SCRUBADDRESSHI 114
- 13.2.2.7 SCRUBCTL 114
- 13.2.2.8 SPAREINTERVAL 116
- 13.2.2.9 RASENABLES 116
- 13.2.2.10 SMISPARECTL 116
- 13.2.2.11 LEAKY_BUCKET_CFG 117
- 13.2.3.1 PXPCAP 120
- 13.2.3.2 DIMMMTR_[0:2] 120
- 0x80, 0x84, 0x88 121
- 13.2.3.3 PXPENHCAP 122
- 13.2.4.1 PXPCAP 125
- 13.2.4.2 PMONCNTR_[0:4] 126
- 13.2.4.3 PMONCNTR_FIXED 126
- 13.2.4.4 PMONCNTRCFG_[0:4] 127
- 13.2.4.5 PMONUNITCTRL 128
- 13.2.4.6 PMONUNITSTATUS 129
- 13.2.4.7 PXPENHCAP 129
- 13.2.4.8 CHN_TEMP_CFG 130
- 13.2.4.9 CHN_TEMP_STAT 131
- 13.2.4.10 DIMM_TEMP_OEM_[0:2] 131
- 13.2.4.11 DIMM_TEMP_TH_[0:2] 132
- 0x140, 0x144, 0x148 133
- 0x130, 0x134, 0x138 133
- 13.2.4.14 DIMMTEMPSTAT_[0:2] 134
- 13.2.4.15 THRT_PWR_DIMM_[0:2] 135
- 13.2.4.16 TCDBP 136
- 13.2.4.17 TCRAP 136
- 13.2.4.18 TCRWP 137
- 13.2.4.19 TCOTHP 139
- 13.2.4.20 TCRFP 140
- 13.2.4.21 TCRFTP 140
- 13.2.4.22 TCSRFTP 141
- 13.2.4.23 TCMR2SHADOW 142
- 13.2.4.24 TCZQCAL 143
- 13.2.4.25 TCSTAGGER_REF 143
- 13.2.4.26 TCMR0SHADOW 143
- 13.2.4.27 RPQAGE 144
- 13.2.4.28 IDLETIME 144
- 13.2.4.29 RDIMMTIMINGCNTL 145
- 13.2.4.30 RDIMMTIMINGCNTL2 146
- 13.2.4.31 TCMRS 147
- 13.2.4.32 MC_INIT_STAT_C 147
- 13.2.5.1 PXPCAP 148
- 13.2.5.2 PXPENHCAP 149
- 13.2.5.3 CORRERRCNT_0 149
- 13.2.5.4 CORRERRCNT_1 150
- 13.2.5.5 CORRERRCNT_2 150
- 13.2.5.6 CORRERRCNT_3 151
- 13.2.5.7 CORRERRTHRSHLD_0 151
- 13.2.5.8 CORRERRTHRSHLD_1 152
- 13.2.5.9 CORRERRTHRSHLD_2 152
- 13.2.5.10 CORRERRTHRSHLD_3 153
- 13.2.5.11 CORRERRORSTATUS 153
- 13.2.5.13 DEVTAG_CNTL_[0:7] 154
- 13.3 Home Agent Registers 155
- 13.3.1.1 TMBAR 156
- Agent Registers 157
- 13.5.1.1 QPIMISCSTAT 158
- 13.5.2.1 PXPCAP 159
- 13.5.2.2 PXPENHCAP 159
- 13.5.2.3 FWDC_LCPKAMP_CFG 160
- 13.6.1.1 CPUNODEID 161
- 13.6.1.2 INTCONTROL 162
- 13.6.1.3 GIDNIDMAP 163
- 13.6.1.4 CORECOUNT 164
- 13.6.1.5 UBOXERRSTS 164
- 13.6.2 Device 11 Function 2 165
- 13.6.3.1 CPUBUSNO 166
- 13.6.3.2 SMICTRL 167
- 13.7.1.3 PACKAGE_POWER_SKU 169
- 13.7.1.6 PACKAGE_TEMPERATURE 171
- 13.7.1.7 P_STATE_LIMITS 171
- 13.7.1.8 TEMPERATURE_TARGET 171
- 13.7.2 Device 10 Function 1 172
- 13.7.2.1 SSKPD 173
- 13.7.2.2 C2C3TT 173
- 13.7.2.3 CSR_DESIRED_CORES 173
- 13.7.3 Device 10 Function 2 174
- 13.7.3.2 DRAM_POWER_INFO 175
- 13.7.3.3 DRAM_ENERGY_STATUS 176
- 13.7.3.6 MCA_ERR_SRC_LOG 177
- 13.7.3.7 THERMTRIP_CONFIG 177
- 13.7.4.1 CAP_HDR 178
- 13.7.4.2 CAPID0 179
- 13.7.4.3 CAPID1 182
- 13.7.4.4 CAPID2 183
- 13.7.4.5 CAPID3 185
- 13.7.4.6 CAPID4 187
- 13.7.4.7 RESOLVED_CORES_MASK 187
- 188 Intel 188
- 14 Integrated I/O (IIO) 189
- Device 3 Function 0-3 PCIe* 190
- 14.2.1 VID 194
- 14.2.2 DID 195
- 14.2.3 PCICMD 195
- 14.2.4 PCISTS 198
- 14.2.5 RID 200
- 14.2.6 CCR 200
- 14.2.7 CLSR 200
- 14.2.8 PLAT 201
- 14.2.9 HDR 201
- 14.2.10 BIST 201
- 14.2.11 PBUS 202
- 14.2.12 SECBUS 202
- 14.2.13 SUBBUS 202
- 14.2.14 IOBAS 203
- 14.2.15 IOLIM 203
- 14.2.16 SECSTS 204
- 14.2.17 MBAS 205
- 14.2.18 MLIM 206
- 14.2.19 PBAS 206
- 14.2.20 PLIM 207
- 14.2.21 PBASU 207
- 14.2.22 PLIMU 208
- 14.2.23 CAPPTR 208
- 14.2.24 INTL 209
- 14.2.25 INTPIN 209
- 14.2.26 BCTRL 209
- 14.2.27 SCAPID 211
- 14.2.28 SNXTPTR 211
- 14.2.29 SVID 211
- 14.2.30 SDID 212
- 14.2.31 DMIRCBAR 212
- 14.2.32 MSICAPID 213
- 14.2.33 MSINXTPTR 213
- 14.2.34 MSIMSGCTL 213
- 14.2.35 MSGADR 214
- 14.2.36 MSGDAT 215
- 14.2.37 MSIMSK 215
- 14.2.38 MSIPENDING 215
- 14.2.39 PXPCAPID 216
- 14.2.40 PXPNXTPTR 216
- 14.2.41 PXPCAP 216
- 14.2.42 DEVCAP 218
- 14.2.43 DEVCTRL 219
- 14.2.44 DEVSTS 221
- 14.2.45 LNKCAP 222
- 14.2.46 LNKCON 224
- 14.2.47 LNKSTS 226
- 14.2.48 SLTCAP 227
- 14.2.49 SLTCON 230
- 14.2.50 SLTSTS 232
- 14.2.51 ROOTCON 233
- 14.2.52 ROOTCAP 236
- 14.2.53 ROOTSTS 236
- 14.2.54 DEVCAP2 237
- 14.2.55 DEVCTRL2 238
- 14.2.56 LNKCAP2 239
- 14.2.57 LNKCON2 241
- 14.2.58 LNKSTS2 243
- 14.2.59 PMCAP 244
- 14.2.60 PMCSR 245
- 14.2.61 XPREUT_HDR_EXT 246
- 14.2.62 XPREUT_HDR_CAP 247
- 14.2.63 XPREUT_HDR_LEF 247
- 14.2.64 ACSCAPHDR 248
- 14.2.65 ACSCAP 248
- 14.2.66 ACSCTRL 249
- 14.2.67 APICBASE 250
- 14.2.68 APICLIMIT 250
- 14.2.69 VSECPHDR 251
- 14.2.70 VSHDR 251
- 14.2.71 ERRCAPHDR 252
- 14.2.72 UNCERRSTS 252
- 14.2.73 UNCERRMSK 253
- 14.2.74 UNCERRSEV 253
- 14.2.75 CORERRSTS 255
- 14.2.76 CORERRMSK 255
- 14.2.77 ERRCAP 256
- 14.2.78 HDRLOG[0:3] 256
- 14.2.79 RPERRCMD 256
- 14.2.80 RPERRSTS 257
- 14.2.81 ERRSID 258
- 14.2.82 PERFCTRLSTS_0 259
- 14.2.83 PERFCTRLSTS_1 260
- 14.2.84 MISCCTRLSTS_0 261
- 14.2.85 MISCCTRLSTS_1 263
- 14.2.86 PCIE_IOU_BIF_CTRL 265
- 14.2.87 DMICTRL 266
- 14.2.88 DMISTS 267
- 14.2.89 ERRINJCAP 267
- 14.2.90 ERRINJHDR 268
- 14.2.91 ERRINJCON 268
- 14.2.92 CTOCTRL 269
- 14.2.93 XPCORERRSTS 269
- 14.2.94 XPCORERRMSK 270
- 14.2.95 XPUNCERRSTS 270
- 14.2.96 XPUNCERRMSK 271
- 14.2.97 XPUNCERRSEV 272
- 14.2.98 XPUNCERRPTR 272
- 14.2.99 UNCEDMASK 272
- 14.2.100 COREDMASK 273
- 14.2.101 RPEDMASK 274
- 14.2.102 XPUNCEDMASK 274
- 14.2.103 XPCOREDMASK 275
- 14.2.104 XPGLBERRSTS 275
- 14.2.105 XPGLBERRPTR 275
- 14.2.106 PXP2CAP 276
- 14.2.107 LNKCON3 277
- 14.2.108 LNERRSTS 277
- 14.2.109 LN[0:3]EQ 278
- 0x25c, 0x25e, 0x260, 0x262 279
- 14.2.110 LN[4:7]EQ 280
- 0x264, 0x266, 0x268, 0x26a 281
- 14.2.111 LN[8:15]EQ 282
- 14.2.112 LER_CAP 284
- 14.2.113 LER_HDR 284
- 14.2.114 LER_CTRLSTS 284
- 14.2.115 LER_UNCERRMSK 286
- 14.2.116 LER_XPUNCERRMSK 287
- 14.2.117 LER_RPERRMSK 287
- 14.2.118 XPPMDL[0:1] 287
- 0x480 , 0x484 288
- 14.2.119 XPPMCL[0:1] 289
- 14.2.120 XPPMDH 289
- 14.2.121 XPPMCH 289
- 14.2.122 XPPMR[0:1] 290
- 0x494, 0x498 291
- 14.2.123 XPPMEVL[0:1] 293
- 0x49c, 0x4a0 294
- 14.2.124 XPPMEVH[0:1] 297
- 14.2.125 XPPMER[0:1] 298
- 14.3.1 DMIVC0RCAP 299
- 14.3.2 DMIVC0RCTL 300
- 14.3.3 DMIVC0RSTS 301
- 14.3.4 DMIVC1RCAP 301
- 14.3.5 DMIVC1RCTL 302
- 14.3.6 DMIVC1RSTS 303
- 14.3.7 DMIVCPRCAP 303
- 14.3.8 DMIVCPRCTL 304
- 14.3.9 DMIVCPRSTS 305
- 14.3.10 DMIVCMRCAP 305
- 14.3.11 DMIVCMRCTL 306
- 14.3.12 DMIVCMRSTS 306
- 14.3.13 DMIVC1CDTTHROTTLE 307
- 14.3.14 DMIVCPCDTTHROTTLE 307
- 14.3.15 DMIVCMCDTTHROTTLE 308
- 14.4 Device 4 Function 0-7 309
- 14.4.1 VID 310
- 14.4.2 DID 310
- 14.4.3 PCICMD 310
- 14.4.4 PCISTS 312
- 14.4.5 RID 313
- 14.4.6 CCR 313
- 14.4.7 CLSR 314
- 14.4.8 HDR 315
- 14.4.9 CB_BAR 315
- 14.4.10 SVID 316
- 14.4.11 SDID 316
- 14.4.12 CAPPTR 316
- 14.4.13 INTL 316
- 14.4.14 INTPIN 317
- 14.4.15 DEVCFG 317
- 14.4.16 MSIXCAPID 318
- 14.4.17 MSIXNXTPTR 318
- 14.4.18 MSIXMSGCTL 319
- 14.4.19 TABLEOFF_BIR 319
- 14.4.20 PBAOFF_BIR 319
- 14.4.21 CAPID 320
- 14.4.22 NEXTPTR 320
- 14.4.23 EXPCAP 320
- 14.4.24 DEVCAP 321
- 14.4.25 DEVCON 322
- 14.4.26 DEVSTS 323
- 14.4.27 DEVCAP2 324
- 14.4.28 DEVCON2 324
- 14.4.29 PMCAP 325
- 14.4.30 PMCSR 325
- 14.4.31 DMAUNCERRSTS 327
- 14.4.32 DMAUNCERRMSK 327
- 14.4.33 DMAUNCERRSEV 327
- 14.4.34 DMAUNCERRPTR 328
- 14.4.35 DMAGLBERRPTR 328
- 14.4.36 CHANERR_INT 329
- 14.4.37 CHANERRMSK_INT 331
- 14.4.38 CHANERRSEV_INT 332
- 14.4.39 CHANERRPTR 333
- 14.5.1 CHANCNT 334
- 14.5.2 XFERCAP 335
- 14.5.3 GENCTRL 335
- 14.5.4 INTRCTRL 335
- 14.5.5 ATTNSTATUS 336
- 14.5.6 CBVER 336
- 14.5.7 INTRDELAY 337
- 14.5.8 CS_STATUS 337
- 14.5.9 DMACAPABILITY 337
- 14.5.10 DCAOFFSET 339
- 14.5.11 CBPRIO 340
- 14.5.12 CHANCTRL 340
- 14.5.13 DMA_COMP 341
- 14.5.14 CHANCMD 341
- 14.5.15 DMACOUNT 342
- 14.5.16 CHANSTS_0 342
- 14.5.17 CHANSTS_1 344
- 14.5.18 CHAINADDR_0 344
- 14.5.19 CHAINADDR_1 344
- 14.5.20 CHANCMP_0 345
- 14.5.21 CHANCMP_1 345
- 14.5.22 CHANERR 345
- 14.5.23 CHANERRMSK 348
- 14.5.24 DCACTRL 348
- 14.5.25 DCA_VER 348
- 14.5.26 DCA_REQID_OFFSET 349
- 14.5.27 QPI_CAPABILITY 349
- 14.5.28 PCIE_CAPABILITY 349
- 14.5.29 QPI_CAP_ENABLE 350
- 14.5.30 PCIE_CAP_ENABLE 350
- 14.5.31 APICID_TAG_MAP 350
- 14.5.32 DCA_REQID[0:1] 352
- 14.5.33 MSGADDR 352
- 14.5.34 MSGUPADDR 353
- 14.5.35 MSGDATA 353
- 14.5.36 VECCTRL 353
- 14.5.37 PENDINGBITS 353
- 14.6 Device 5 Function 0 354
- 14.6.1 VID 356
- 14.6.2 DID 356
- 14.6.3 PCICMD 356
- 14.6.4 PCISTS 357
- 14.6.5 RID 358
- 14.6.6 CCR 358
- 14.6.7 CLSR 359
- 14.6.8 HDR 359
- 14.6.9 SVID 359
- 14.6.10 SDID 360
- 14.6.11 CAPPTR 360
- 14.6.12 INTL 360
- 14.6.13 INTPIN 360
- 14.6.14 PXPCAPID 361
- 14.6.15 PXPNXTPTR 361
- 14.6.16 PXPCAP 361
- 14.6.17 HDRTYPECTRL 361
- 14.6.18 MMCFG_BASE 362
- 14.6.19 MMCFG_LIMIT 362
- 14.6.20 TSEG 363
- 14.6.23 GENPROTRANGE2_BASE 364
- 14.6.24 GENPROTRANGE2_LIMIT 364
- 14.6.25 TOLM 365
- 14.6.26 TOHM 365
- 14.6.27 NCMEM_BASE 366
- 14.6.28 NCMEM_LIMIT 366
- 14.6.29 MENCMEM_BASE 367
- 14.6.30 MENCMEM_LIMIT 367
- 14.6.31 CPUBUSNO 367
- 14.6.32 LMMIOL_BASE 368
- 14.6.33 LMMIOL_LIMIT 368
- 14.6.34 LMMIOH_BASE 369
- 14.6.35 LMMIOH_LIMIT 369
- 14.6.36 CIPCTRL 369
- 14.6.37 CIPSTS 372
- 14.6.38 CIPDCASAD 372
- 14.6.39 CIPINTRC 373
- 14.6.40 CIPINTRS 374
- 14.6.41 VTBAR 375
- 14.6.42 VTGENCTRL 375
- 14.6.43 VTGENCTRL2 376
- 14.6.44 IOTLBPARTITION 377
- 14.6.45 VTUNCERRSTS 379
- 14.6.46 VTUNCERRMSK 380
- 14.6.47 VTUNCERRSEV 381
- 14.6.48 VTUNCERRPTR 382
- 14.6.49 IIOMISCCTRL 382
- 14.6.50 LTDPR 388
- 14.6.51 IRP_MISC_DFX0 389
- 14.6.52 IRP_MISC_DFX1 390
- 14.6.53 IRP[0:1]DELS 391
- 14.6.54 IRP[0:1]DBGRING0 392
- 14.6.55 IRP[0:1]DBGRING1 392
- 14.6.56 IRPSPAREREGS 392
- 14.6.57 IRP[0:1]RNG 392
- 0x830, 0x834 393
- 14.6.58 IRPEGCREDITS 394
- 14.6.59 IRP_MISC_DFX2 396
- 14.6.60 IRP_MISC_DFX3 398
- 14.7.1 VTD[0:1]_VERSION 401
- 14.7.2 VTD[0:1]_CAP 401
- 14.7.3 VTD[0:1]_EXT_CAP 402
- 0x10 , 0x1010 403
- 14.7.4 VTD[0:1]_GLBCMD 404
- 0x18, 0x1018 405
- 14.7.5 VTD[0:1]_GLBSTS 406
- 14.7.6 VTD[0:1]_ROOTENTRYADD 407
- 14.7.7 VTD[0:1]_CTXCMD 407
- 0x28 , 0x1028 408
- 14.7.8 VTD[0:1]_FLTSTS 409
- 14.7.9 NONISOCH_FLTEVTCTRL 410
- 14.7.10 NONISOCH_FLTEVTDATA 410
- 14.7.11 VTD[0:1]_FLTEVTADDR 411
- 14.7.13 VTD[0:1]_PMEN 411
- 0x68 , 0x1068 412
- 0x6c, 0x106c 412
- 0x70 , 0x1070 412
- 0x78 , 0x1078 413
- 0x80 , 0x1080 413
- 0x88, 0x1088 413
- 0x90 , 0x1090 414
- 0x9c , 0x109c 414
- 14.7.23 NONISOCH_INVEVTDATA 415
- VT-d Fault Record 416
- 14.7.29 VTD[0:1]_INVADDRREG 417
- 14.7.30 VTD[0:1]_IOTLBINV 418
- 0x208 , 0x1208 419
- 14.8 Device 5 Function 2 420
- 14.8.1 VID 422
- 14.8.2 DID 423
- 14.8.3 PCICMD 423
- 14.8.4 PCISTS 424
- 14.8.5 RID 425
- 14.8.6 CCR 425
- 14.8.7 CLSR 425
- 14.8.8 HDR 426
- 14.8.9 SVID 426
- 14.8.10 SDID 426
- 14.8.11 CAPPTR 426
- 14.8.12 INTL 427
- 14.8.13 INTPIN 427
- 14.8.14 PXPCAPID 427
- 14.8.15 PXPNXTPTR 427
- 14.8.16 PXPCAP 428
- 14.8.17 IRPPERRSV 428
- 14.8.18 IIOERRSV 429
- 14.8.19 MIERRSV 430
- 14.8.20 PCIERRSV 430
- 14.8.21 SYSMAP 431
- 14.8.22 VIRAL 432
- 14.8.23 ERRPINCTL 433
- 14.8.24 ERRPINSTS 433
- 14.8.25 ERRPINDAT 434
- 14.8.26 VPPCTL 435
- 14.8.27 VPPSTS 436
- 14.8.28 VPPFREQ 436
- 14.8.29 VPPMEM 437
- 14.8.30 GNERRMASK 438
- 14.8.31 GFERRMASK 439
- 14.8.32 GCERRMASK 440
- 14.8.33 GCERRST 442
- 14.8.34 GCFERRST, GCNERRST 443
- 14.8.35 GNERRST 444
- 14.8.36 GFERRST 445
- 14.8.37 GERRCTL 446
- 14.8.38 GSYSST 448
- 14.8.39 GSYSCTL 448
- 14.8.40 GFFERRST, GFNERRST 448
- 14.8.41 GNFERRST, GNNERRST 449
- 14.8.42 IRPP[0:1]ERRST 449
- 14.8.43 IRPP[0:1]ERRCTL 450
- 0x234, 0x2b4 451
- IRP0: 0x238, 0x23c 451
- 14.8.45 IRPP[0:1]FFERRHD[0:3] 452
- IRP0: 0x250, 0x254 465
- 14.8.47 IRPP[0:1]NFERRHD[0:3] 466
- 14.8.48 IRPP[0:1]ERRCNTSEL 466
- 14.8.49 IRPP[0:1]ERRCNT 466
- 14.8.50 IIOERRST 467
- 14.8.51 IIOERRCTL 467
- 0x308, 0x31c 468
- 14.8.53 IIOFFERRHD_[0:3] 469
- 14.8.55 IIONFERRHD_[0:3] 470
- 14.8.56 IIOERRCNTSEL 470
- 14.8.57 IIOERRCNT 471
- 14.8.58 MIERRST 471
- 14.8.59 MIERRCTL 472
- 14.8.60 MIFFERRST, MIFNERRST 472
- 14.8.61 MIFFERRHDR_[0:3] 472
- 0x38c Size: 128 bits 473
- 14.8.62 MINFERRST, MINNERRST 474
- 14.8.63 MINFERRHDR_[0:3] 474
- 14.9 Device 5 Function 4 475
- 14.9.1 VID 476
- 14.9.2 DID 476
- 14.9.3 PCICMD 477
- 14.9.4 PCISTS 478
- 14.9.5 RID 479
- 14.9.6 CCR 479
- 14.9.7 CLSR 479
- 14.9.8 HDR 480
- 14.9.9 MBAR 480
- 14.9.10 SVID 480
- 14.9.11 SID 481
- 14.9.12 CAPPTR 481
- 14.9.13 INTLIN 481
- 14.9.14 INTPIN 481
- 14.9.15 ABAR 482
- 14.9.16 PXPCAP 482
- 14.9.17 SNAPSHOT_INDEX 483
- 14.9.18 SNAPSHOT_WINDOW 483
- 14.9.19 IOAPICTETPC 484
- 14.9.20 PMCAP 485
- 14.9.21 PMCSR 485
- 14.9.22 IOADSELS0 486
- 14.9.23 IOADSELS1 487
- 14.9.24 IOINTSRC0 487
- 14.9.25 IOINTSRC1 488
- 14.9.26 IOREMINTCNT 488
- 14.9.27 IOREMGPECNT 489
- 14.9.28 FAUXGV 489
- 14.10.1 INDEX 490
- 14.10.2 WINDOW 490
- 14.10.3 EOI 490
- 14.10.4.1 APICID__WINDOW 492
- 14.10.4.2 VER__WINDOW 492
- 14.10.4.3 ARBID__WINDOW 493
- 14.10.4.4 BCFG__WINDOW 493
- 14.10.4.5 RTL[0:23]__WINDOW 493
- 14.10.4.6 RTH[0:23]__WINDOW 495
- 14.11.1 VID 496
- 14.11.2 DID 497
- 14.11.3 PCICMD 497
- 14.11.4 PCISTS 498
- 14.11.5 RID 499
- 14.11.6 CCR 499
- 14.11.7 CLSR 499
- 14.11.8 PLAT 500
- 14.11.9 HDR 500
- 14.11.10 BIST 500
- 14.11.11 SVID 500
- 14.11.12 SDID 501
- 14.11.13 CAPPTR 501
- 14.11.14 INTL 501
- 14.11.15 INTPIN 501
- 14.11.16 MINGNT 502
- 14.11.17 MAXLAT 502
- 14.11.18 PXPCAP 502
- 14.11.19 RX_CTLE_PEAK_GEN2 503
- 14.11.20 RX_CTLE_PEAK_GEN3 503
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