Intel CL8064701528402 Datový list

329366-002Intel® Core™ i7 Processor Family for LGA2011 SocketDatasheet – Volume 1 of 2Supporting Desktop Intel® Core™ i7-4960X Extreme Edition Process

Introduction10 Datasheet1.2 Supported Technologies •Intel® Virtualization Technology (Intel® VT)•Intel® Virtualization Technology (Intel® VT) for Dir

Datasheet 100 Processor Land ListingBE51 VSS GNDBE7 VCC PWRBE9 VCC PWRBF10 VCC PWRBF12 VCC PWRBF14 VCC PWRBF16 VCC PWRBF2 VCC PWRBF4 VCC PWRBF42 VSS G

101 DatasheetProcessor Land ListingBM16 VSS GNDBM2 VSS GNDBM4 VSS GNDBM42 VTTD PWRBM44 RSVDBM46 RSVDBM6 VSS GNDBM8 VSS GNDBN1 VCC PWRBN11 VCC PWRBN13

Datasheet 102 Processor Land ListingBW11 VSS GNDBW13 VSS GNDBW15 VSS GNDBW17 VSS GNDBW3 VCC_SENSE OBW43 TDI CMOS IBW5 VSS GNDBW7 VSS GNDBW9 DDR0_DQ[28

103 DatasheetProcessor Land ListingCB2 DDR0_DQ[08] SSTL I/OCB20 DDR01_RCOMP[2] Analog ICB22 MEM_HOT_C01_N ODCMOS I/OCB24 DDR0_ODT[4] SSTL OCB26 DDR0_C

Datasheet 104 Processor Land ListingCF12 VSS GNDCF14 VSS GNDCF16 DDR0_DQS_DN[17] SSTL I/OCF20 DDR0_CKE[4] SSTL OCF22 DDR0_CLK_DN[3] SSTL OCF24 DDR0_CL

105 DatasheetProcessor Land ListingCJ5 DDR0_DQ[11] SSTL I/OCJ51 VSS GNDCJ7 DDR0_DQ[06] SSTL I/OCJ9 VSS GNDCK10 VSS GNDCK12 DDR0_DQ[16] SSTL I/OCK14 DD

Datasheet 106 Processor Land ListingCN57 VSS GNDCN7 VSS GNDCN9 VSS GNDCP10 DDR1_DQ[19] SSTL I/OCP12 VSS GNDCP14 DDR1_DQS_DN[12] SSTL I/OCP16 VSS GNDCP

107 DatasheetProcessor Land ListingCU27 DDR1_ODT[4] SSTL OCU29 DDR1_DQ[36] SSTL I/OCU3 VSS GNDCU31 DDR1_DQS_DP[13] SSTL I/OCU33 DDR1_DQ[38] SSTL I/OCU

Datasheet 108 Processor Land ListingD10 DDR3_DQS_DP[04] SSTL I/OD12 DDR3_DQ[32] SSTL I/OD14 DDR3_ODT[4] SSTL OD16 DDR3_CS_N[8] SSTL OD18 DDR3_MA[10] S

109 DatasheetProcessor Land ListingDC9 DDR1_DQS_DN[01] SSTL I/ODD10 VSS GNDDD12 VSS GNDDD14 VSS GNDDD18 VCCD_01 PWRDD20 VCCD_01 PWRDD22 VCCD_01 PWRDD2

Datasheet 11 Introduction1.3.2 PCI Express*• The PCI Express* port(s) are fully-compliant with the PCI Express* Base Specification, Revision 3.0 (PCIe

Datasheet 110 Processor Land ListingF28 DDR3_DQS_DP[17] SSTL I/OF32 DDR3_DQ[19] SSTL I/OF34 DDR3_DQ[17] SSTL I/OF36 VSS GNDF38 DDR3_DQ[06] SSTL I/OF4

111 DatasheetProcessor Land ListingJ37 DDR3_DQS_DP[01] SSTL I/OJ39 VSS GNDJ41 VSS GNDJ43 PE1A_TX_DP[1] PCIEX3 OJ45 PE1A_TX_DP[3] PCIEX3 OJ47 PE1B_TX_D

Datasheet 112 Processor Land ListingM38 DDR3_DQS_DP[10] SSTL I/OM4 DDR3_DQS_DP[07] SSTL I/OM40 DDR3_DQ[12] SSTL I/OM42 VSS GNDM44 VSS GNDM46 VSS GNDM4

113 DatasheetProcessor Land ListingR49 PE3B_TX_DP[7] PCIEX3 OR5 VSS GNDR51 PE3B_TX_DP[5] PCIEX3 OR53 PRDY_N CMOS OR55 VSS GNDR7 VSS GNDR9 DDR2_DQ[54]

Datasheet 114 Processor Land Listing§W11 DDR2_DQS_DP[06] SSTL I/OW13 VSS GNDW15 RSVDW17 DDR2_CS_N[8] SSTL OW19 DDR2_ODT[1] SSTL OW21 DDR2_CLK_DN[2] SS

Datasheet 115 Package Mechanical Specifications9 Package Mechanical SpecificationsThe processor is in a Flip-Chip Land Grid Array (FCLGA12) package th

Boxed Processor Specifications116 Datasheet10 Boxed Processor Specifications10.1 IntroductionIntel boxed processors are intended for system integrato

Introduction12 Datasheet1.3.3 Direct Media Interface Gen 2 (DMI2)• Serves as the chip-to-chip interface to the PCH• The DMI2 port supports x4 link wi

Datasheet 13 Introduction1.3.4 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication channel bet

Introduction14 Datasheet1.6 Package SummaryThe processor socket type is noted as LGA2011. The processor package is a 52.5 x 45 mm FC-LGA package (LG

Datasheet 15 IntroductionIntel® VT-dIntel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a hardware assist, under system softw

Introduction16 Datasheet1.8 Related DocumentsRefer to the following documents for additional information.Uncore The portion of the processor comprisi

Datasheet 17 Introduction§Table 1-3. Public Specifications Document Document Number / LocationAdvanced Configuration and Power Interface Specification

Interfaces18 Datasheet2 InterfacesThis chapter describes the functional behaviors supported by the processor. Topics covered include:• System Memory

Datasheet 19 Interfaces2.2 PCI Express* InterfaceThis section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Expr

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH Intel® PRODUCTS. NO LICENSE, Express* OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO

Interfaces20 Datasheet2.2.1.1 Transaction LayerThe upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer'

Datasheet 21 Interfacesregion can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configur

Interfaces22 DatasheetThe interface design was optimized for interfacing to Intel processor and chipset components in both single processor and multi

Datasheet 23 Technologies3 TechnologiesThis chapter covers the following technologies:•Intel® Virtualization Technology (Intel® VT)• Security Technolo

Technologies24 Datasheet3.1.2 Intel® VT-x FeaturesThe processor core supports the following Intel VT-x features:• Extended Page Tables (EPT)— hardwar

Datasheet 25 Technologies3.1.3.1 Intel® VT-d Features SupportedThe processor supports the following Intel VT-d features:• Root entry, context entry, a

Technologies26 Datasheet3.2 Security Technologies3.2.1 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) InstructionsThese instru

Datasheet 27 Technologies3.4 Intel® Turbo Boost TechnologyIntel Turbo Boost Technology is a feature that allows the processor to opportunistically and

Technologies28 Datasheet3.6 Intel® Advanced Vector Extensions (Intel® AVX)Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD e

Datasheet 29 Technologies• Compatibility – Intel AVX is backward compatible with previous ISA extensions including Intel SSE4: — Existing Intel SSE ap

Datasheet 3Table of Contents1Introduction...

Power Management30 Datasheet4 Power ManagementThis chapter provides information on the following power management topics:• Advanced Configuration and

Datasheet 31 Power ManagementNotes:1. Package C7 is not supported.2. All package states are defined to be "E" states – such that the states

Power Management32 Datasheet4.1.3 Integrated Memory Controller (IMC) States4.1.4 Direct Media Interface Gen 2 (DMI2) / PCI Express* Link StatesNote:

Datasheet 33 Power Management4.1.5 G, S, and C State Combinations4.2 Processor Core / Package Power ManagementWhile executing code, Enhanced Intel Spe

Power Management34 Datasheet4.2.2 Low-Power Idle StatesWhen the processor is idle, low-power idle states (C-states) are used to save power. More powe

Datasheet 35 Power ManagementNote:1. If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher.4.2.3

Power Management36 Datasheet4.2.4 Core C-statesThe following are general rules for all core C-states, unless specified otherwise:• A core C-state is

Datasheet 37 Power Management4.2.4.6 Delayed Deep C-StatesThe Delayed Deep C-states (DDCst) feature on this processor replaces the “C-state auto-demot

Power Management38 DatasheetThere is also a concept of Execution Allowed (EA). When EA status is 0, the cores in a socket are in C3 or a deeper state

Datasheet 39 Power Management4.2.5.2 Package C1/C1E StateNo additional power reduction actions are taken in the package C1 state. However, if the C1E

4 Datasheet4.2 Processor Core / Package Power Management ...334.2.1 Enhanced Intel® SpeedStep® Tec

Power Management40 Datasheet4.2.5.5 Package C6 StateA processor enters the package C6 low-power state when:• At least one core is in the C6 state.• T

Datasheet 41 Power Management4.3.1 CKE Power-DownThe CKE input land is used to enter and exit different power-down modes. The memory controller has a

Power Management42 Datasheet4.3.2.2 Self-Refresh ExitSelf-refresh exit can be either a message from an external unit (PCU in most cases, but also pos

Datasheet 43 Thermal Management Specifications5 Thermal Management SpecificationsThe processor requires a thermal solution to maintain temperatures wi

Signal Descriptions44 Datasheet6 Signal DescriptionsThis chapter describes the processor signals. The signals are arranged in functional groups accor

Datasheet 45 Signal Descriptions6.2 PCI Express* Based Interface SignalsNote: PCI Express* Ports 1, 2, and 3 signals are receive and transmit differen

Signal Descriptions46 DatasheetPE2C_TX_DN[11:8]PE2C_TX_DP[11:8]PCIe Transmit Data OutputPE2D_TX_DN[15:12]PE2D_TX_DP[15:12]PCIe Transmit Data OutputTa

Datasheet 47 Signal Descriptions6.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals6.4 Platform Environment Control Interface (PECI)

Signal Descriptions48 Datasheet6.7 Serial Voltage Identification (SVID) Signals6.8 Processor Asynchronous Sideband and Miscellaneous SignalsTMSTest M

Datasheet 49 Signal DescriptionsPROCHOT_NProcessor Hot: PROCHOT_N will go active when the processor temperature monitoring sensor detects that the pro

Datasheet 5Figures1-1 Processor Platform Block Diagram Example...91-2 PCI Express* Lane Part

Signal Descriptions50 DatasheetTXT_AGENT Intel® Trusted Execution Technology (Intel® TXT) Agent: This is a strap signal: 0 = Default. The socket is n

Datasheet 51 Signal Descriptions6.9 Processor Power and Ground Supplies§ §§ §Table 6-14. Power and Ground Signals Signal Name Description VCCVariable

Electrical Specifications52 Datasheet7 Electrical SpecificationsThis chapter covers the following topics:• Processor Signaling• Signal Group Summary•

Datasheet 53 Electrical Specifications7.1.4 Platform Environmental Control Interface (PECI)PECI is an Intel proprietary interface that provides a comm

Electrical Specifications54 DatasheetClock multiplying within the processor is provided by the internal phase locked loop (PLL) that requires a const

Datasheet 55 Electrical Specifications7.1.8.2 Decoupling GuidelinesDue to its large number of transistors and high internal clock speeds, the processo

Electrical Specifications56 Datasheet• SetVID_slow (5mV/µs for VCC, 2.5mV/µs for VSA/VCCD), and • Slew Rate Decay (downward voltage only and it is a

Datasheet 57 Electrical Specificationsreduce the switching frequency or pulse skip, or change to asynchronous regulation. For example, typical power s

Electrical Specifications58 Datasheet3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase coun

Datasheet 59 Electrical Specifications7.1.9 Reserved or Unused SignalsAll Reserved (RSVD) signals must not be connected. Connection of these signals t

6 Datasheet7-10 Voltage Specifications...647-11 Current Specific

Electrical Specifications60 DatasheetDDR3 Control Signals2Single endedCMOS1.5v OutputDDR{0/1/2/3}_CS_N[9:0]DDR{0/1/2/3}_ODT[5:0]DDR{0/1/2/3}_CKE[5:0]

Datasheet 61 Electrical SpecificationsNotes:1. Refer to Chapter 6 for signal description details.2. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channe

Electrical Specifications62 DatasheetNotes:1. Refer to Table 7-17 for details on the RON (Buffer on Resistance) value for this signal.7.3 Power-On Co

Datasheet 63 Electrical SpecificationsNotes:1. For functional operation, all processor electrical, signal quality, mechanical, and thermal specificati

Electrical Specifications64 Datasheet2. These ratings apply to the Intel component and do not include the tray or packaging.3. Failure to adhere to t

Datasheet 65 Electrical Specifications5. The VTTA, and VTTD voltage specification requirements are measured across the remote sense pin pairs (VTTD_SE

Electrical Specifications66 Datasheet7.5.2 Die Voltage ValidationCore voltage (VCC) overshoot events at the processor must meet the specifications in

Datasheet 67 Electrical Specifications7.5.3 Signal DC SpecificationsDC specifications are defined at the processor pads, unless otherwise noted. DC sp

Electrical Specifications68 Datasheet2. The voltage rail VCCD which will be set to 1.50V or 1.35V nominal depending on the voltage of all DIMMs conne

Datasheet 69 Electrical Specifications4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.5. VHavg

Datasheet 7Revision History§Revision NumberDescription Date001 • Initial release September 2013002• Chapter , "1 Introduction 9,"— Section 1

Electrical Specifications70 Datasheet1. VTT refers to instantaneous VTT.2. Measured at 0.31*VTT3. Vin between 0V and VTT4. These are measured between

Datasheet 71 Electrical Specifications7.5.3.1 PCI Express* DC SpecificationsThe processor DC specifications for the PCI Express* are available in the

Processor Land Listing72 Datasheet8 Processor Land ListingThis chapter provides the processor land lists. Table 8-1 is a listing of all processor lan

73 DatasheetProcessor Land ListingTable 8-1. Land List by Land Name (Sheet 1 of 42)Land NameLand No.Buffer TypeDirectionBCLK0_DN CM44 CMOS IBCLK0_DP C

Datasheet 74 Processor Land ListingDDR0_DQ[31] CF10 SSTL I/ODDR0_DQ[32] CE31 SSTL I/ODDR0_DQ[33] CC31 SSTL I/ODDR0_DQ[34] CE35 SSTL I/ODDR0_DQ[35] CC3

75 DatasheetProcessor Land ListingDDR0_ODT[2] CH28 SSTL ODDR0_ODT[3] CF28 SSTL ODDR0_ODT[4] CB24 SSTL ODDR0_ODT[5] CC27 SSTL ODDR0_PAR_ERR_N CC21 SSTL

Datasheet 76 Processor Land ListingDDR1_DQ[50] CR41 SSTL I/ODDR1_DQ[51] CU41 SSTL I/ODDR1_DQ[52] CT36 SSTL I/ODDR1_DQ[53] CV36 SSTL I/ODDR1_DQ[54] CT4

77 DatasheetProcessor Land ListingDDR2_CLK_DN[2] W21 SSTL ODDR2_CLK_DN[3] W23 SSTL ODDR2_CLK_DP[0] AB24 SSTL ODDR2_CLK_DP[1] AB22 SSTL ODDR2_CLK_DP[2]

Datasheet 78 Processor Land ListingDDR2_DQS_DN[08] AB28 SSTL I/ODDR2_DQS_DN[09] W39 SSTL I/ODDR2_DQS_DN[10] AC39 SSTL I/ODDR2_DQS_DN[11] T32 SSTL I/OD

79 DatasheetProcessor Land ListingDDR3_DQ[03] E37 SSTL I/ODDR3_DQ[04] F40 SSTL I/ODDR3_DQ[05] D40 SSTL I/ODDR3_DQ[06] F38 SSTL I/ODDR3_DQ[07] A37 SSTL

Introduction8 Datasheet1 IntroductionThe Intel® Core™ i7 processor family for LGA2011 socket are the next generation of 64-bit, multi-core desktop pr

Datasheet 80 Processor Land ListingDDR3_DQS_DP[09] E39 SSTL I/ODDR3_DQS_DP[10] M38 SSTL I/ODDR3_DQS_DP[11] D34 SSTL I/ODDR3_DQS_DP[12] N31 SSTL I/ODDR

81 DatasheetProcessor Land ListingPE1B_RX_DP[5] K54 PCIEX3 IPE1B_RX_DP[6] J57 PCIEX3 IPE1B_RX_DP[7] K56 PCIEX3 IPE1B_TX_DN[4] K46 PCIEX3 OPE1B_TX_DN[5

Datasheet 82 Processor Land ListingPE3A_TX_DP[1] J51 PCIEX3 OPE3A_TX_DP[2] R47 PCIEX3 OPE3A_TX_DP[3] P48 PCIEX3 OPE3B_RX_DN[4] AB50 PCIEX3 IPE3B_RX_DN

83 DatasheetProcessor Land ListingRSVD BM44RSVD BM46RSVD BN47RSVD BP44RSVD BP46RSVD BR43RSVD BR47RSVD BT44RSVD BU43RSVD BY46RSVD C53RSVD CA45RSVD CD44

Datasheet 84 Processor Land ListingVCC AN3 PWRVCC AN5 PWRVCC AN7 PWRVCC AN9 PWRVCC AP10 PWRVCC AP12 PWRVCC AP14 PWRVCC AP16 PWRVCC AP2 PWRVCC AP4 PWRV

85 DatasheetProcessor Land ListingVCC BG9 PWRVCC BH10 PWRVCC BH12 PWRVCC BH14 PWRVCC BH16 PWRVCC BH2 PWRVCC BH4 PWRVCC BH6 PWRVCC BH8 PWRVCC BJ1 PWRVC

Datasheet 86 Processor Land ListingVCC_SENSE BW3 OVCCD_01 CD20 PWRVCCD_01 CD22 PWRVCCD_01 CD24 PWRVCCD_01 CD26 PWRVCCD_01 CD28 PWRVCCD_01 CJ19 PWRVCCD

87 DatasheetProcessor Land ListingVSS A7 GNDVSS AA11 GNDVSS AA29 GNDVSS AA3 GNDVSS AA31 GNDVSS AA39 GNDVSS AA5 GNDVSS AA55 GNDVSS AA9 GNDVSS AB14 GNDV

Datasheet 88 Processor Land ListingVSS AT12 GNDVSS AT14 GNDVSS AT16 GNDVSS AT2 GNDVSS AT4 GNDVSS AT46 GNDVSS AT52 GNDVSS AT6 GNDVSS AT8 GNDVSS AU45 GN

89 DatasheetProcessor Land ListingVSS BR57 GNDVSS BT46 GNDVSS BT48 GNDVSS BT50 GNDVSS BT52 GNDVSS BT54 GNDVSS BT56 GNDVSS BU45 GNDVSS BU51 GNDVSS BW1

Datasheet 9 Introduction1.1 Processor Feature Details• Up to 6 execution cores• Each core supports two threads (Intel® Hyper-Threading Technology), up

Datasheet 90 Processor Land ListingVSS CH48 GNDVSS CH50 GNDVSS CH52 GNDVSS CH54 GNDVSS CH6 GNDVSS CJ11 GNDVSS CJ17 GNDVSS CJ29 GNDVSS CJ3 GNDVSS CJ43

91 DatasheetProcessor Land ListingVSS CW35 GNDVSS CW37 GNDVSS CW39 GNDVSS CW5 GNDVSS CW51 GNDVSS CW53 GNDVSS CW55 GNDVSS CW57 GNDVSS CW7 GNDVSS CY10 G

Datasheet 92 Processor Land ListingVSS H34 GNDVSS H38 GNDVSS H40 GNDVSS H52 GNDVSS H54 GNDVSS H8 GNDVSS J11 GNDVSS J27 GNDVSS J31 GNDVSS J33 GNDVSS J3

93 DatasheetProcessor Land ListingVSS W51 GNDVSS W53 GNDVSS W9 GNDVSS Y10 GNDVSS Y12 GNDVSS Y28 GNDVSS Y30 GNDVSS Y32 GNDVSS Y36 GNDVSS Y38 GNDVSS Y40

Datasheet 94 Processor Land ListingTable 8-2. Land List by Land Number (Sheet 1 of 42)Land No.Land NameBuffer TypeDirectionA11 DDR3_DQ[33] SSTL I/OA1

95 DatasheetProcessor Land ListingAC41 DDR2_DQ[12] SSTL I/OAC43 PE3D_TX_DP[14] PCIEX3 OAC45 PE3D_TX_DN[12] PCIEX3 OAC47 PE3C_TX_DN[9] PCIEX3 OAC49 PE3

Datasheet 96 Processor Land ListingAF54 VSS GNDAF56 VSS GNDAF58 PE2B_RX_DN[7] PCIEX3 IAF6 VSS GNDAF8 DDR2_DQ[42] SSTL I/OAG1 VSS GNDAG11 DDR2_DQ[34] S

97 DatasheetProcessor Land ListingAL15 VCC PWRAL17 VCC PWRAL3 VCC PWRAL43 VSS GNDAL45 VSS GNDAL49 VSS GNDAL5 VCC PWRAL51 VSS GNDAL53 VSS GNDAL55 RSVDA

Datasheet 98 Processor Land ListingAT44 BPM_N[1] ODCMOS I/OAT46 VSS GNDAT48 BIST_ENABLE CMOS IAT52 VSS GNDAT54 PE2B_TX_DN[7] PCIEX3 OAT56 PE2D_RX_DN[1

99 DatasheetProcessor Land ListingB38 DDR3_DQS_DN[00] SSTL I/OB40 DDR3_DQ[00] SSTL I/OB42 DMI_TX_DP[0] PCIEX OB44 DMI_TX_DP[2] PCIEX OB46 RSVDB48 DMI_