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Intel ARCHITECTURE IA-32 manuály

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Intel ARCHITECTURE IA-32 Uživatelský manuál (636 strany)


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Tabulka s obsahem

IA-32 Intel

1

Architecture

1

Software Developer’s Manual

1

CONTENTS FOR VOLUME 3A AND 3B

3

Vol. 3A v

5

Vol. 3A vii

7

Vol. 3A ix

9

Vol. 3A xi

11

Vol. 3A xiii

13

Vol. 3A xv

15

Vol. 3A xvii

17

Vol. 3A xix

19

Vol. 3A xxi

21

Vol. 3A xxiii

23

Vol. 3A xxv

25

Vol. 3A xxvii

27

Vol. 3A xxix

29

Vol. 3A xxxi

31

Vol. 3A xxxiii

33

About This Manual

35

CHAPTER 1

37

ABOUT THIS MANUAL

37

1.3 NOTATIONAL CONVENTIONS

40

1.3.1 Bit and Byte Order

41

1.3.3 Instruction Operands

42

1.3.5 Segmented Addressing

43

1.3.7 Exceptions

44

1.4 RELATED LITERATURE

45

System Architecture

47

Overview

47

CHAPTER 2

49

SYSTEM ARCHITECTURE OVERVIEW

49

Linear Address

51

Tab leDirectory

52

2.1.5 Memory Management

55

2.1.6 System Registers

56

2.1.7 Other System Resources

58

2.2 MODES OF OPERATION

58

2.4.4 Task Register (TR)

64

2.5 CONTROL REGISTERS

64

Counters

76

Protected-Mode

79

CHAPTER 3

81

Logical Address

82

3.2 USING SEGMENTS

83

3.2.1 Basic Flat Model

83

3.2.2 Protected Flat Model

83

Figure 3-2. Flat Model

84

3.2.3 Multi-Segment Model

85

3.2.5 Paging and Segmentation

86

3.3 PHYSICAL ADDRESS SPACE

86

Vol. 3A 3-7

87

3.4.2 Segment Selectors

88

3.4.3 Segment Registers

89

Vol. 3A 3-11

91

3.4.5 Segment Descriptors

92

Vol. 3A 3-13

93

3-14 Vol. 3A

94

3-16 Vol. 3A

96

3.5 SYSTEM DESCRIPTOR TYPES

97

3-20 Vol. 3A

100

3.6.1 Paging Options

101

ADDRESSING

102

Page Directory

103

3.7.4 Memory Aliasing

105

3-28 Vol. 3A

108

Vol. 3A 3-29

109

MECHANISM

110

Vol. 3A 3-31

111

Addressing Enabled

114

Vol. 3A 3-35

115

PAGING MECHANISM

117

Vol. 3A 3-39

119

Physical Addr

120

3-42 Vol. 3A

122

Vol. 3A 3-43

123

MOV CR3, EAX

126

Vol. 3A 3-47

127

3-48 Vol. 3A

128

Protection

129

CHAPTER 4

131

PROTECTION

131

PAGE-LEVEL PROTECTION

132

4.3 LIMIT CHECKING

135

• The type field

136

4.5 PRIVILEGE LEVELS

138

Figure 4-3. Protection Rings

139

SEGMENTS

141

REGISTER

143

From Various Privilege Levels

146

• Call gates

147

• Trap gates

147

• Interrupt gates

147

• Task gates

147

4.8.3 Call Gates

148

Segment Selector

151

4.8.5 Stack Switching

153

4.9 PRIVILEGED INSTRUCTIONS

162

4.10 POINTER VALIDATION

162

Instructions)

164

Instruction)

164

4.10.5 Checking Alignment

167

4.11 PAGE-LEVEL PROTECTION

167

4.11.1 Page-Protection Flags

168

4.11.3 Page Type

168

• IA-32e mode

170

4.13.3 Reserved Bit Checking

173

• IA32_EFER.NXE = 1

174

Interrupt and

175

Exception Handling

175

CHAPTER 5

177

5.3 SOURCES OF INTERRUPTS

178

5.3.1 External Interrupts

178

5-4 Vol. 3A

180

• Machine-check exceptions

181

5.6 PROGRAM OR TASK RESTART

182

Vol. 3A 5-7

183

5.7.1 Handling Multiple NMIs

184

Vol. 3A 5-9

185

INTERRUPTS

186

5-12 Vol. 3A

188

• Task-gate descriptor

189

• Interrupt-gate descriptor

189

• Trap-gate descriptor

189

5-16 Vol. 3A

192

5-18 Vol. 3A

194

5.12.2 Interrupt Tasks

195

5.13 ERROR CODE

197

5.14.1 64-Bit Mode IDT

198

Vol. 3A 5-23

199

5.14.3 IRET in IA-32e Mode

200

5.14.5 Interrupt Stack Table

201

5-26 Vol. 3A

202

Vol. 3A 5-27

203

Interrupt 2—NMI Interrupt

205

5-30 Vol. 3A

206

Vol. 3A 5-31

207

5-32 Vol. 3A

208

Vol. 3A 5-33

209

5-34 Vol. 3A

210

Vol. 3A 5-35

211

5-36 Vol. 3A

212

Vol. 3A 5-39

215

Exception Class Fault

216

Description

216

5-42 Vol. 3A

218

Vol. 3A 5-43

219

5-44 Vol. 3A

220

Vol. 3A 5-45

221

5-46 Vol. 3A

222

Vol. 3A 5-47

223

5-48 Vol. 3A

224

Vol. 3A 5-49

225

5-50 Vol. 3A

226

Vol. 3A 5-51

227

MOV SS, AX

229

MOV SP, StackTop

229

5-54 Vol. 3A

230

Vol. 3A 5-55

231

5-56 Vol. 3A

232

5-58 Vol. 3A

234

Vol. 3A 5-59

235

5-60 Vol. 3A

236

Vol. 3A 5-61

237

Vol. 3A 5-63

239

5-64 Vol. 3A

240

Task Management

241

CHAPTER 6

243

TASK MANAGEMENT

243

6.1.2 Task State

244

6.1.3 Executing a Task

245

• Task-state segment (TSS)

246

• TSS descriptor

246

• Task register

246

6.2.2 TSS Descriptor

249

6.2.4 Task Register

251

Figure 6-5. Task Register

252

6.2.5 Task-Gate Descriptor

253

6.3 TASK SWITCHING

254

6.4 TASK LINKING

258

Figure 6-8. Nested Tasks

259

6.4.2 Modifying Task Linkages

260

6.5 TASK ADDRESS SPACE

261

Multiple-Processor

267

Management

267

CHAPTER 7

269

MULTIPLE-PROCESSOR MANAGEMENT

269

7.1 LOCKED ATOMIC OPERATIONS

270

7.1.2 Bus Locking

271

7-6 Vol. 3A

274

7.2 MEMORY ORDERING

275

7.4 SERIALIZING INSTRUCTIONS

282

7.5.1 BSP and AP Processors

284

Vol. 3A 7-19

287

7-20 Vol. 3A

288

• Cores per Package

292

7.8 INTEL

294

HYPER-THREADING TECHNOLOGY

294

ARCHITECTURE

294

7.8.2 APIC Functionality

296

7.8.8 IA32_MISC_ENABLE MSR

298

7.8.9 Memory Ordering

298

7.8.12 Self Modifying Code

299

7.9 DUAL-CORE ARCHITECTURE

301

7.9.4 IA32_MISC_ENABLE MSR

302

Platform

304

Hyper-Threading Technology

305

7-38 Vol. 3A

306

Vol. 3A 7-39

307

7-40 Vol. 3A

308

Vol. 3A 7-41

309

7-42 Vol. 3A

310

Vol. 3A 7-43

311

7-44 Vol. 3A

312

7.11.1 HLT Instruction

313

7.11.2 PAUSE Instruction

314

Spin_Lock:

317

JE Get_Lock

317

7-50 Vol. 3A

318

Vol. 3A 7-51

319

7-52 Vol. 3A

320

Advanced

323

Programmable

323

Interrupt Controller

323

CHAPTER 8

325

ADVANCED PROGRAMMABLE

325

INTERRUPT CONTROLLER (APIC)

325

8-2 Vol. 3A

326

3-Wire APIC Bus

327

MP systems

328

8.2 SYSTEM BUS VS. APIC BUS

329

8.3 THE INTEL

329

82489DX EXTERNAL APIC

329

THE APIC, AND THE XAPIC

329

8.4 LOCAL APIC

329

8-6 Vol. 3A

330

8-10 Vol. 3A

334

63 071011 8912

335

8.4.6 Local APIC ID

336

8.4.7 Local APIC State

336

Vol. 3A 8-13

337

8-14 Vol. 3A

338

8.5 HANDLING LOCAL INTERRUPTS

339

8.5.1 Local Vector Table

339

Vol. 3A 8-17

341

8.5.2 Valid Interrupt Vectors

342

8.5.3 Error Handling

343

8.5.4 APIC Timer

344

8-22 Vol. 3A

346

8-24 Vol. 3A

348

Vol. 3A 8-25

349

8-28 Vol. 3A

352

8-30 Vol. 3A

354

8-32 Vol. 3A

356

8.8 HANDLING INTERRUPTS

357

Processors

357

Pentium Processors)

359

vector / 16

360

Figure 8-21. EOI Register

364

8.9 SPURIOUS INTERRUPT

365

8.10.1 Bus Message Formats

367

8-44 Vol. 3A

368

31 20 19 12 11 4 3 2 1 0

368

Vol. 3A 8-45

369

8-46 Vol. 3A

370

31 16 15 14 13 11 10 8 7 0

370

Vol. 3A 8-47

371

8-48 Vol. 3A

372

Processor

373

Management and

373

Initialization

373

CHAPTER 9

375

PROCESSOR MANAGEMENT AND

375

INITIALIZATION

375

9-2 Vol. 3A

376

9.2 X87 FPU INITIALIZATION

380

9.3 CACHE ENABLING

382

Vol. 3A 9-9

383

OPERATION

384

9.7.1 Real-Address Mode IDT

385

9.7.2 NMI Interrupt Handling

385

9-12 Vol. 3A

386

9.8.3 Initializing Paging

387

9-14 Vol. 3A

388

Vol. 3A 9-15

389

9-16 Vol. 3A

390

9.9 MODE SWITCHING

391

9-18 Vol. 3A

392

Vol. 3A 9-19

393

9-20 Vol. 3A

394

FFFF FFFFH

395

FFFF FFF0H

395

FFFF 0000H

395

64K EPROM

395

9.10.1 Assembler Usage

396

9.10.2 STARTUP.ASM Listing

397

9-24 Vol. 3A

398

Vol. 3A 9-25

399

9-26 Vol. 3A

400

Vol. 3A 9-27

401

9-28 Vol. 3A

402

Vol. 3A 9-29

403

162-172 of List File)

404

RAM_START

405

9.10.3 MAIN.ASM Source Code

407

9.10.4 Supporting Files

407

9-34 Vol. 3A

408

9.11.1 Microcode Update

410

Vol. 3A 9-41

415

Table 9-10. Processor Flags

416

Vol. 3A 9-43

417

; Offset of microcode update

418

Vol. 3A 9-45

419

9-46 Vol. 3A

420

Vol. 3A 9-47

421

Access: Read/Write

421

Vol. 3A 9-49

423

9-50 Vol. 3A

424

Vol. 3A 9-51

425

9-52 Vol. 3A

426

Vol. 3A 9-53

427

9-58 Vol. 3A

432

Vol. 3A 9-59

433

9-60 Vol. 3A

434

Table 9-16. Mnemonic Values

435

Memory Cache

439

CHAPTER 10

441

MEMORY CACHE CONTROL

441

10.2 CACHING TERMINOLOGY

444

10.3.2 Choosing a Memory Type

449

10.4 CACHE CONTROL PROTOCOL

450

10.5 CACHE CONTROL

450

and P6 family

452

Pentium II Processors

456

10.5.3 Preventing Caching

458

10.6 SELF-MODIFYING CODE

461

AND P6 FAMILY PROCESSORS)

462

10.8 EXPLICIT CACHING

462

10.10 STORE BUFFER

464

Register Pair

471

Vol. 3A 10-33

473

10-34 Vol. 3A

474

10.11.5 MTRR Initialization

475

≠ FirstType

476

Vol. 3A 10-37

477

10-38 Vol. 3A

478

10.12.2 IA32_CR_PAT MSR

482

10.12.4 Programming the PAT

483

Technology

487

System Programming

487

CHAPTER 11

489

MMX™ TECHNOLOGY SYSTEM

489

PROGRAMMING

489

REGISTERS

492

• System exceptions:

493

Exceptions

494

11.6 DEBUGGING MMX CODE

494

11-8 Vol. 3A

496

SSE, SSE2 and SSE3

497

CHAPTER 12

499

• CPUID.1:EDX.SSE[bit 25] = 1

500

• CPUID.1:ECX.SSE3[bit 0] = 1

500

SSE3, EM, MP, and TS

501

• Memory Access Exceptions:

502

Vol. 3A 12-5

503

12-6 Vol. 3A

504

OR CONTEXT SWITCHES

505

CONTEXT SWITCHES

505

12-8 Vol. 3A

506

• Clears the TS flag

508

Power and Thermal

509

CHAPTER 13

511

POWER AND THERMAL MANAGEMENT

511

IA32_MPERF (Addr: E7H)

512

IA32_APERF (Addr: E8H)

512

Vol. 3A 13-3

513

MANAGEMENT

514

13.4.2 Thermal Monitor

516

Thermal Status Log

518

Clock Modulation Facilities

521

16222327

522

16222324

523

Machine Check

525

Architecture

525

CHAPTER 14

527

MACHINE-CHECK ARCHITECTURE

527

14.3 MACHINE-CHECK MSRS

528

. . . .

531

14.3.3 Mapping of the Pentium

537

14-12 Vol. 3A

538

14.6.1 Simple Error Codes

539

14.6.2 Compound Error Codes

540

Vol. 3A 14-19

545

14.7.3 Pentium

546

Vol. 3A 14-21

547

8086 Emulation

549

CHAPTER 15

551

8086 EMULATION

551

15.2 VIRTUAL-8086 MODE

557

15.2.7 Sensitive Instructions

564

15.2.8 Virtual-8086 Mode I/O

564

IN VIRTUAL-8086 MODE

565

Mixing 16-Bit

579

CHAPTER 16

581

MIXING 16-BIT AND 32-BIT CODE

581

16.4.4 Parameter Translation

588

IA-32 Architecture

591

Compatibility

591

CHAPTER 17

593

17.2. RESERVED BITS

594

THROUGH SOFTWARE

594

17.5. INTEL MMX TECHNOLOGY

595

17.10. DUAL-CORE TECHNOLOGY

596

PROCESSORS

596

17.13. OBSOLETE INSTRUCTIONS

598

17.14. UNDEFINED OPCODES

598

17.16. STACK OPERATIONS

599

17.16.1 PUSH SP

599

17.17. X87 FPU

600

17.17.2 x87 FPU Status Word

601

17.17.3 x87 FPU Control Word

602

17.17.4 x87 FPU Tag Word

602

17.17.5 Data Types

602

Vol. 3A 17-11

603

17-12 Vol. 3A

604

Vol. 3A 17-13

605

17-14 Vol. 3A

606

Vol. 3A 17-15

607

17-16 Vol. 3A

608

Vol. 3A 17-17

609

17.17.9 Obsolete Instructions

610

Vol. 3A 17-19

611

17.20. CONTROL REGISTERS

613

17-22 Vol. 3A

614

Vol. 3A 17-23

615

17.22. DEBUG FACILITIES

616

Vol. 3A 17-25

617

17-26 Vol. 3A

618

17.25. INTERRUPTS

619

17.25.2 NMI Interrupts

619

17.25.3 IDT Limit

620

Family and Pentium Processors

621

17.27. TASK SWITCHING AND TSS

621

17.27.2 TSS Selector Writes

622

Offset FH from beginning of

623

17-32 Vol. 3A

624

17.29. PAGING

625

17.29.1 Large Pages

625

17.29.2 PCD and PWT Flags

625

17.30. STACK OPERATIONS

626

17.30.2 Error Code Pushes

627

17.32.1 Segment Wraparound

628

Vol. 3A 17-37

629

17.34. BUS LOCKING

630

17.35. BUS HOLD

631

17-40 Vol. 3A

632

Vol. 3A 17-41

633

17-42 Vol. 3A

634

INTEL SALES OFFICES

635




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