Intel LE80537GF0414M Datový list Strana 24
- Strana / 97
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Summary Tables of Changes
24 Specification Update
Number
Stepping
Stepping
Stepping
Plans
ERRATA
B-2
L-2
A-1
AH38
X
X
X
Plan Fix
FXSAVE/FXRSTOR Instructions which Store to the End of
the Segment and Cause a Wrap to a Misaligned Base
Address (Alignment <= 0x10h) May Cause FPU Instruction
or Operand Pointer Corruption
AH39
X
X
Fixed
Cache Data Access Request from One Core Hitting a
Modified Line in the L1 Data Cache of the Other Core May
Cause Unpredictable System Behavior
AH40
X
X
X
Plan Fix
PREFETCHh Instruction Execution under Some Conditions
May Lead to Processor Livelock
AH41
X
X
X
Plan Fix
PREFETCHh Instructions May Not Be Executed when
Alignment Check (AC) Is Enabled
AH42
X
X
X
Plan Fix
Upper 32 Bits of the FPU Data (Operand) Pointer in the
FXSAVE Memory Image May Be Unexpectedly All 1‟s after
FXSAVE
AH43
X
X
Fixed
Concurrent Multi-processor Writes to Non-dirty Page May
Result in Unpredictable Behavior
AH44
X
X
X
Plan Fix
Performance Monitor IDLE_DURING_DIV (18h) Count May
Not Be Accurate
AH45
X
X
X
No Fix
Values for LBR/BTS/BTM Will Be Incorrect after an Exit
from SMM
AH46
X
X
Fixed
Shutdown Condition May Disable Non-Bootstrap Processors
AH47
X
X
Fixed
SYSCALL Immediately after Changing EFLAGS.TF May Not
Behave According to the New EFLAGS.TF
AH48
X
X
X
No Fix
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
AH49
X
X
X
No Fix
VM Bit Is Cleared on Second Fault Handled by Task Switch
from Virtual-8086 (VM86)
AH50
X
X
X
Plan Fix
IA32_FMASK Is Reset during an INIT
AH51
X
X
X
No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
AH52
X
X
X
No Fix
Last Branch Records (LBR) Updates May Be Incorrect after
a Task Switch
AH53
X
X
X
No Fix
IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
AH54
X
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
AH55
X
X
X
Plan Fix
Using Memory Type Aliasing with Memory Types WB/WT
May Lead to Unpredictable Behavior
AH56
X
X
X
Plan Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
- Including Intel 1
- Specification Update 2
- Contents 3
- Revision History 4
- 6 Specification Update 6
- Preface 7
- Nomenclature 8
- Specification Update 9 9
- Identification Information 10
- Table 3. Intel 13
- 945 Express Chipset Family 13
- Component Markings 13
- 14 Specification Update 14
- Table 2. Intel 14
- 965 Express Chipset Family 14
- 16 Specification Update 16
- Table 1. Intel 17
- Celeron 17
- 18 Specification Update 18
- Summary Tables of Changes 19
- Specification Update 21 21
- Errata for Intel 22
- 24 Specification Update 24
- 26 Specification Update 26
- 28 Specification Update 28
- Based on Mobile Intel 29
- 30 Specification Update 30
- 32 Specification Update 32
- 34 Specification Update 34
- 38 Specification Update 38
- May Terminate Early 38
- 40 Specification Update 40
- Specification Update 43 43
- Specification Update 45 45
- Not Be Accurate 46
- Specification 47
- Address Translations 47
- Specification Update 49 49
- Specification Update 51 51
- Invocation 52
- Specification Update 53 53
- Be Incorrect 54
- Specification Update 55 55
- Specification Update 57 57
- Accurate 59
- Specification Update 61 61
- Specification Update 63 63
- Shootdown 65
- Specification Update 67 67
- Address 68
- IA32_DEBUGCTL[12] Is Set 69
- Software Interrupts 71
- Specification Update 73 73
- Specification Update 75 75
- Specification Update 77 77
- Specification Update 79 79
- Instructions as Branches 81
- Signaled 82
- Information 83
- AH108. Overlap of an Intel 84
- VM Exit 84
- Count Some Transitions 85
- Memory-Ordering Violations 86
- Specification Update 87 87
- Shutdown 88
- Specification Update 89 89
- 90 Specification Update 90
- Erratum Affecting Only Intel 91
- Core™2 Duo Mobile 91
- Processors on Mobile Intel 91
- Be Able to Enter Intel 92
- Enhanced Deeper Sleep 92
- AH6P Activation of Intel 93
- Dynamic 93
- Specification Changes 94
- Specification Update 95 95
- Specification Clarifications 96
- Documentation Changes 97
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