Intel 80526KZ800256 Datový list stáhnout pdf (Strana 98)

APPENDIX

Figure 42. PWRGD Implementation

10.1.41 REQ[4:0]# (I/O)

The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents. They

are asserted by the current bus owner over two clock cycles to define the currently active transaction type.

+5V

OCVR_EN

OCVR

OCVR_OK

CPU_PWR_GD

OCVR_EN

PWR_GD_PS

Vcc

smb(3.3V)

CPU_PWRGD

Other PS’s,

VRMs, OCVRs

with

open-drain

PWR_GDs

VRM

PWRGDOUTEN

CPU_RESET#

Delay

Reset Logic

3V->5V

buffer

(7408)

3.3V

Pull-up for Pentium® III Xeon™ Processor

3.3V

Processor

Core

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 104 105

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Intel 80526KZ800256 Datový list Strana 98