Intel 80526KZ667256 Datový list

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PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS103.3 Decoupling GuidelinesDue to the large number of tra

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX100The STPCLK# (Stop Clock) signal, when asserted, causes processors to en

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX101pins. The power supply must supply the voltage that is requested by the

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX102Table 54. Input SignalsName Active Level Clock Signal Group Qualified

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX103Table 55. I/O Signals (Single Driver)Name Active Level Clock Signal G

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS11NOTE:The frequency multipliers supported are shown in

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS12A20M#IGNNE#LINT1/NMILINT0/INTRProcessors1KΩ2.5 VSet Rat

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS13recommended range of values to support for the processo

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS143.6 System Bus Unused Pins and Test PinsUnless otherwi

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS15Table 3. Processor pin GroupsGroup Name SignalsAGTL+

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS16A Debug Port is described in Chapter 8. The Debug Port

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS17voltage clamp, with the exception of BCLK, PICCLK and P

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS18Table 6. Current Specifications 1,10Symbol Parameter M

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS19Table 6. Current Specifications 1,10Symbol Parameter M

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache2Information in this document is provided in connection with Intel products. No li

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS20Table 8. CMOS, TAP, Clock and APIC Signal Groups, DC

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS21Table 9. SMBus Signal Group, DC Specifications at th

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS22Table 11 Internal Parameters for the AGTL+ BusSymbol Pa

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS23Table 12. System Bus AC Specifications (Clock) at the

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS24Table 13. AGTL+ Signal Group, System Bus AC Specificat

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS25Table 15. System Bus AC Specifications (Reset Conditi

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS26Table 17. System Bus AC Specifications (TAP Connectio

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS27Table 18. SMBus Signal Group, AC Specifications at the

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS28SCLK2.46V0.84VThTlTrTfTrT54TfT55T52ThT53Tl====2.97V0.84

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS29BCLKRESET#Configuration(A20M#, IGNNE#,LINT[1:0])Configu

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache3TABLE OF CONTENTSPRODUCT FEATURES...

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS30TCKTDI, TMSInputSignalsTDOOutputSignalsP6CB766a1.25VTvT

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY314. SIGNAL QUALITYSignals driven on the Pentium® III Xeon™ processo

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY324.2.1 AGTL+ Ringback Tolerance SpecificationsTable 21 provides t

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY334.2.2.1 Overshoot/Undershoot MagnitudeOvershoot magnitude describe

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY34• If multiple overshoots and/or multiple undershoots occur, measu

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY35Figure 13. Maximum Acceptable Overshoot/Undershoot Waveform1,2,3,

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY36UndershootOvershootSettling LimitSettling LimitRising-EdgeRingback

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY37Intel recommends that platforms meet the Absolute Maximum Specific

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheSIGNAL QUALITY384.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINESettling limit

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES395. PROCESSOR FEATURES5.1 Low Power States and Clock ControlThe

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache46.2.3 MEASUREMENTS FOR THERMAL SPECIFICATIONS...

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES402. Auto HALT Power Down StateBCLK running.Snoops and interrup

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES415.1.5 SLEEP STATE — STATE 5The Sleep state is a very low powe

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES42R10K1/16W5%R10K1/16W5%R10K1/16W5%R10K1/16W5%R10K1/16W5%SDASCLW

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES43Systems implementing analog sensing should read the PIROM firs

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES44Table 26. processor Information ROM FormatOffset/Section # o

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES4516 L2 Cache Size 16-Bit binary number (in Kbytes)8 Reserved16

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES465.2.2 SCRATCH EEPROMAlso available on the SMBus is an EEPRO

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES47Table 28. Receive Byte SMBus PacketS DeviceAddressR/W*A* Data

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES48uniquely determined for each unit. The procedure causes each u

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES491. This is an 8-bit field. The device that sent the alert wil

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache510.1.35 PICCLK (I) ...

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES505.2.6.3 Status RegisterThe status register shown in Table 37

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES51Table 38. Thermal Sensor Configuration RegisterBit Name Reset

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CachePROCESSOR FEATURES52The thermal sensor latches the SA1 and SA2 signals at power up

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheTHERMAL SPECIFICATIONS536. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONSThe Pen

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheTHERMAL SPECIFICATIONS54 Table 42 Power Dissipat

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheTHERMAL SPECIFICATIONS556.1.2 PLATE FLATNESS SPECIFICATIONThe thermal plate flatn

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheTHERMAL SPECIFICATIONS56between the thermal plate and heat sink. The other control

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheTHERMAL SPECIFICATIONS576.2.3 MEASUREMENTS FOR THERMAL SPECIFICATIONS6.2.3.1 Pla

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS587. MECHANICAL SPECIFICATIONSPentium® III Xeon™ processo

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS59Figure 23. S.E.C. Cartridge Cooling Solution Attach De

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache61. INTRODUCTIONThe Pentium® III Xeon™ processor at 600 MHz+, like the Pentium® Pr

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS60Figure 24. S.E.C. Cartridge Retention Enabling Details

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS61Figure 25. SEC Cartridge Retention Enabling Details1.

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS627.1 WeightThe maximum weight of a Pentium® III Xeon™ pr

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS63Figure 28. Front View of Connector Mating DetailsNOTES

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS647.3 Substrate Edge Finger Signal ListingTable 44 is the

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS65Table 44. Signal Listing in Order by Pin NumberPinNo.

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS66Table 44. Signal Listing in Order by Pin NumberPinNo.

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS67Table 44. Signal Listing in Order by Pin NumberPinNo.

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS68Table 45. Signal Listing in Order by Pin NamePinNo. Pi

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS69PinNo. Pin Name Signal Buffer TypeA92 D#[05] AGTL+ I/OB

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheTERMINOLOGY72. TERMINOLOGYIn this document, a ‘#’ symbol after a signal name refer

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS70PinNo. Pin Name Signal Buffer TypeA132 DEFER# AGTL+ Inp

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS71PinNo. Pin Name Signal Buffer TypeA9 SELFSB0 CMOS Input

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS72PinNo. Pin Name Signal Buffer TypeB118 VCC_L2 (N/C) L2

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheMECHANICAL SPECIFICATIONS73PinNo. Pin Name Signal Buffer TypeA34 VSS GroundA37 VSS

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS748. INTEGRATION TOOLSThe integration tool set for Pentium® III X

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS75The ITP will connect to the system through the debug port. Reco

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS768.1.5 DEBUG PORT SIGNAL DESCRIPTIONSTable 46 describes the debu

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS77Table 46. Debug Port Pinout Description and Requirements1Name

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS78Table 46. Debug Port Pinout Description and Requirements1Name

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS79The DBRESET# output signal from the ITP is an open drain with a

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheTERMINOLOGY8• SC 330 processor — refers to the Pentium II Xeon processor, Pentiu

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS80Figure 31. TCK with individual buffering schemeThe ITP buffer b

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheINTEGRATION TOOLS81V CCTAPSC 330.1ProcessorTDITDOSC 330.1ProcessorTDITDOTDITDODebu

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheBOXED PROCESSOR SPECIFICATIONS829. BOXED PROCESSOR SPECIFICATIONS9.1 Introduction

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheBOXED PROCESSOR SPECIFICATIONS83BDACFigure 34. Side View Space Requirements for t

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheBOXED PROCESSOR SPECIFICATIONS84EFFigure 35. Front View Space Requirements for th

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheBOXED PROCESSOR SPECIFICATIONS859.3 Thermal SpecificationsThis section describes

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheBOXED PROCESSOR SPECIFICATIONS86perform with very little local airflow. Therefor

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheBOXED PROCESSOR SPECIFICATIONS871.54.24Figure 38. Side View Space Recommendation

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheBOXED PROCESSOR SPECIFICATIONS88also recommended that the power header be consist

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX8910. APPENDIXThis appendix provides an alphabetical listing of all Pentiu

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheELECTRICAL SPECIFICATIONS93. ELECTRICAL SPECIFICATIONS3.1 System Bus and VREFThe P

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX9010.1.6 BCLK (I)The BCLK (Bus Clock) is a 2.5V tolerant signal that deter

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX91The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the syst

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX92Table 51. BR[3] and BR[1:0]# Signals Rotating Interconnect,2-Way System

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX9310.1.21 FERR# (O)The FERR# (Floating-point Error) signal is asserted whe

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX9410.1.28 INTR - see LINT[0]10.1.29 LINT[1:0] (I)The LINT[1:0] (Local APIC

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX9510.1.36 PICD[1:0] (I/O)The PICD[1:0] (APIC Data) signals are used for bi

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX96OCVR_OKVout (OCVR)Vin (OCVR)90% of Vin Nominal2.8/5/12VVCC_CPURESET#VR

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX97Figure 42. PWRGD Implementation10.1.41 REQ[4:0]# (I/O)The REQ[4:0]# (Req

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX98The RS[2:0]# (Response Status) signals are driven by the response agent

PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 CacheAPPENDIX99Processor Pin Location Pin Name FunctionalityA7 SELFSB1 Output,Frequency