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Hodnocené. / 5. Na základě hodnocení zákazníků
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 47
System Register Organization—Intel
®
Quark Core
4.4.1.1 Control Register 0 (CR0)
CR0, shown in Figure 13, contains 10 bits for control and status purposes. The function
of the bits in CR0 can be categorized as follows:
•Intel
®
Quark SoC X1000 Core Operating Modes: PG, PE (Table 10)
• On-Chip Cache Control Modes: CD, NW (Table 11)
• On-Chip Floating-Point Unit: NE, TS, EM, TS (Table 12 and Table 13). (Also applies
for the Intel
®
Quark SoC X1000 Core.)
• Alignment Check Control: AM
• Supervisor Write Protect: WP
Figure 13. Control Registers
- Quark SoC X1000 Core 1
- 2 Order Number: 329679-001US 2
- Revision History 3
- Contents 4
- 1.0 About this Manual 17
- 1.2 Notation Conventions 18
- 1.3 Special Terminology 19
- 1.4 Related Documents 20
- 2.0 Intel 21
- 3.0 Architectural Overview 22
- 3.3.1 Address Spaces 23
- 3.3.2 Segment Register Usage 24
- 3.4 I/O Space 25
- 3.5 Addressing Modes 25
- Example: MOV ECX, [EAX+24] 26
- Example: ADD EAX, TABLE[ESI] 26
- A5159-01 27
- 3.6 Data Types 28
- 3.6.1.1 Unsigned Data Types 29
- 3.6.1.2 Signed Data Types 29
- 3.6.1.3 BCD Data Types 30
- 3.6.1.5 String Data Types 30
- 3.6.1.6 ASCII Data Types 31
- 3.6.1.7 Pointer Data Types 32
- 3.7 Interrupts 33
- 3.7.2 Interrupt Processing 34
- 3.7.3 Maskable Interrupt 34
- 3.7.4 Non-Maskable Interrupt 35
- 3.7.5 Software Interrupts 36
- 3.7.7 Instruction Restart 37
- 3.7.8 Double Fault 38
- 4.1 Register Set Overview 39
- 4.2 Floating-Point Registers 39
- 4.3.2 Instruction Pointer 41
- 4.3.3 Flags Register 41
- 4.3.4 Segment Registers 44
- 4.4 System-Level Registers 45
- 4.4.1 Control Registers 46
- A5150-01 53
- 4.5.2 Floating-Point Tag Word 54
- A5152-01 55
- IP Offset 59
- Tag Word 60
- 16-Bit Protected Mode Format 60
- 4.5.5 FPU Control Word 61
- 4.6 Debug and Test Registers 62
- 4.7 Register Accessibility 62
- 4.7.1 FPU Register Usage 63
- 4.9 Intel 64
- 5.0 Real Mode Architecture 65
- 5.2 Memory Addressing 66
- 5.3 Reserved Locations 66
- 5.4 Interrupts 67
- 5.5 Shutdown and Halt 67
- 6.1 Addressing Mechanism 68
- 6.2 Segmentation 69
- 6.2.2 Terminology 70
- 6.2.3 Descriptor Tables 70
- 6.2.4.2 Intel 72
- ≤ limit 74
- 1Writeable (W) 74
- Offset 31...16 P 76
- 6.2.4.7 Selector Fields 77
- 6.3 Protection 81
- 6.3.3.1 Task Privilege 82
- Figure 36. Intel 84
- 6.3.3.4 Privilege Validation 85
- 6.3.3.5 Descriptor Access 85
- 6.3.5 Call Gates 87
- 6.3.6 Task Switching 88
- 6.4.2.1 Page Mechanism 91
- 6.4.2.3 Page Directory 92
- 6.4.2.4 Page Tables 92
- 6.4.3.1 PDPTE Registers 93
- 6.4.4 #GP Faults for Intel 100
- 6.4.5 Access Rights 100
- 6.4.9 Page-Fault Exceptions 104
- 6.4.10 Paging Operation 106
- 6.5 Virtual 8086 Environment 107
- 6.5.5 Interrupt Handling 110
- 7.0 On-Chip Cache 114
- Quark SoC X1000 Core Cache 115
- 7.2 Cache Control 116
- 7.3 Cache Line Fills 117
- 7.4 Cache Line Invalidations 118
- 7.5 Cache Replacement 118
- 7.6 Page Cacheability 119
- Quark SoC X1000 Core and 121
- Processor Page Cacheability 121
- 7.7 Cache Flushing 122
- 7.8 Write-Back Enhanced Intel 123
- Quark SoC X1000 Core Write 123
- Back Cache Architecture 123
- Enhanced Intel 125
- 8.1 SMM Overview 127
- 8.2 Terminology 127
- A5237-01 128
- 8.3.2 SMI# Active (SMIACT#) 129
- A5232-01 130
- 8.3.3.1 SMRAM State Save Map 131
- Register Writeable? 132
- 8.3.4 Exit From SMM 133
- 8.4.2 Processor Environment 135
- 8.5 SMM Features 138
- 8.5.3 I/O Instruction Restart 139
- 8.5.4 SMM Base Relocation 140
- 8.6.1 SMRAM Interface 141
- 8.6.2 Cache Flushes 142
- A5238-01 143
- Quark SoC X1000 Core System 144
- A5240-01 145
- 8.6.2.2 Snoop During SMM 146
- 8.7.1 SMM Code Considerations 147
- 8.7.2 Exception Handling 148
- 8.7.3 Halt During SMM 148
- 9.0 Hardware Interface 149
- 9.2 Signal Descriptions 150
- 9.2.3 Data Lines (D[31:0]) 151
- 9.2.4 Parity 151
- 9.2.5 Bus Cycle Definition 152
- 9.2.6 Bus Control 153
- 9.2.8.1 Reset Input (RESET) 154
- 9.2.9 Bus Arbitration Signals 156
- 9.2.9.4 Backoff Input (BOFF#) 157
- 9.2.11 Cache Control 158
- 9.2.13 RESERVED# 159
- Other Enhanced Bus Features 161
- 9.2.17.2 Cache Flush (FLUSH#) 162
- 9.2.17.4 Soft Reset (SRESET) 163
- 9.2.18.1 Test Clock (TCK) 164
- 9.3.1 Interrupt Logic 166
- 9.3.2 NMI Logic 166
- 9.3.3 SMI# Logic 166
- 9.4 Write Buffers 167
- 9.5 Reset and Initialization 169
- (Sheet 1 of 2) 170
- (Sheet 2 of 2) 171
- 9.6 Clock Control 174
- During Stop Grant State 176
- 9.6.4.1 Normal State 177
- 9.6.4.2 Stop Grant State 177
- 4. Auto HALT Power Down State 178
- 1. Normal State 178
- 2. Stop Grant State 178
- 5. Stop Clock Snoop State 178
- 3. Stop Clock State 178
- 9.6.4.3 Stop Clock State 179
- 9.6.5.1 Normal State 180
- 9.6.5.2 Stop Grant State 181
- 9.6.5.3 Stop Clock State 182
- 10.0 Bus Operation 184
- Physical Memory 185
- I/O Space 185
- BE2# BE1# BE0# 186
- BHE# BLE# 186
- 10.1.5 Operand Alignment 192
- 10.2 Bus Arbitration Logic 193
- 10.3.1.1 No Wait States 196
- 10.3.2.1 Burst Cycles 198
- 242202-033 200
- 10.3.3 Cacheable Cycles 201
- 242202-035 203
- 242202-036 204
- 10.3.4 Burst Mode Details 205
- 242202-038 206
- 242202-039 207
- 242202-067 208
- 10.3.5 8- and 16-Bit Cycles 209
- 242202-069 210
- 10.3.6 Locked Cycles 211
- 10.3.7 Pseudo-Locked Cycles 212
- 10.3.8 Invalidate Cycles 213
- 242202-091 214
- 242202-092 214
- Address, Data and 216
- Control Bus 216
- 10.3.9 Bus Hold 217
- 242202-146 218
- 10.3.10 Interrupt Acknowledge 219
- 10.3.11 Special Bus Cycles 220
- BRDY# or RDY# 221
- ADDR Data 221
- 10.3.12 Bus Cycle Restart 222
- 242202-147 223
- 10.3.13 Bus States 224
- Quark SoC X1000 225
- 10.4.2 Burst Cycles 227
- 10.4.3.2 Snoop under AHOLD 230
- 242202-150 231
- 242202-151 232
- Fill Cont 233
- 242202-153 234
- 10.4.3.4 Snoop under BOFF# 235
- Linefill 236
- 40 04C80C8 236
- 10.4.3.5 Snoop under HOLD 237
- 10.4.4 Locked Cycles 239
- 242202-158 240
- 10.4.4.1 Snoop/Lock Collision 241
- 10.4.6 Pseudo Locked Cycles 242
- Write Back Cycle 243
- 11.0 Debugging Support 246
- 12.0 Instruction Set Summary 252
- 12.2 Instruction Encoding 253
- (No “s-i-b” Byte Present) 259
- 12.2.5 Intel 263
- 12.2.5.2 RDMSR 264
- 12.2.5.3 RDTSC 264
- 12.2.5.4 WRMSR 264
- 12.3 Clock Count Summary 265
- CCCC = Jump on cccc 272
- 18 2 R,7,22 273
- 17 2 R,7,22 274
- 2( 281
- Table 95. Intel 291
- Appendix B Testability 296
- B.1.2 Cache Testability Write 297
- B.1.3 Cache Testability Read 298
- B.1.4 Flush Cache 299
- B.2.3 TLB Write Test 303
- B.3 Intel 304
- Quark SoC X1000 Core JTAG 304
- B.3.1.2 Run-Test/Idle State 305
- B.3.1.3 Select-DR-Scan State 305
- B.3.1.4 Capture-DR State 306
- B.3.1.5 Shift-DR State 306
- B.3.1.6 Exit1-DR State 306
- B.3.1.7 Pause-DR State 306
- B.3.1.8 Exit2-DR State 306
- B.3.1.15 Exit2-IR State 308
- B.3.1.16 Update-IR State 308
- C.1 CPUID Instruction 309
- C.2 Intel 311
- Quark SoC X1000 Stepping 311
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