Intel Galileo Gen 2 Board Specifikace

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Strany 1 - Quark SoC X1000 Core

Order Number: 329679-001USIntel® Quark SoC X1000 CoreDeveloper’s ManualOctober 2013

Strany 2 - 2 Order Number: 329679-001US

Intel® Quark Core—ContentsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201310 Order Number: 329679-001US10.3.11.2Shutdown Indication Cycle ..

Strany 3 - Revision History

Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013100 Order Number: 329679-001US6.4.4 #GP Faults

Strany 4 - Contents

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 101Protected Mode Architecture—Intel® Quark CoreIf CR4.SMEP = 1,

Strany 5

Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013102 Order Number: 329679-001US— The I/D bit of

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 103Protected Mode Architecture—Intel® Quark CoreThe R/W and U/S b

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013104 Order Number: 329679-001USReading a new ent

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 105Protected Mode Architecture—Intel® Quark CoreFigure 46 illustr

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013106 Order Number: 329679-001US• I/D flag (bit 4

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 107Protected Mode Architecture—Intel® Quark CoreNote: Even though

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013108 Order Number: 329679-001US6.5.2 Virtual 808

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 109Protected Mode Architecture—Intel® Quark CoreThe paging hardwa

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 11Contents—Intel® Quark Core12.2.5.3 RDTSC ...

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013110 Order Number: 329679-001USNote that the I/O

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 111Protected Mode Architecture—Intel® Quark CoreAn Intel® Quark S

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013112 Order Number: 329679-001USThe VM bit can be

Strany 17 - 1.0 About this Manual

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 113Protected Mode Architecture—Intel® Quark Core3. Push the legac

Strany 18 - 1.2 Notation Conventions

Intel® Quark Core—On-Chip CacheIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013114 Order Number: 329679-001US7.0 On-Chip CacheThe Intel® Qua

Strany 19 - 1.3 Special Terminology

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 115On-Chip Cache—Intel® Quark CoreThe Write-Back Enhanced Intel®

Strany 20 - 1.4 Related Documents

Intel® Quark Core—On-Chip CacheIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013116 Order Number: 329679-001US7.2 Cache ControlControl of the

Strany 21 - 2.0 Intel

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 117On-Chip Cache—Intel® Quark CoreCD=1, NW=1The 1,1 state is best

Strany 22 - 3.0 Architectural Overview

Intel® Quark Core—On-Chip CacheIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013118 Order Number: 329679-001US7.4 Cache Line InvalidationsThe

Strany 23 - 3.3.1 Address Spaces

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 119On-Chip Cache—Intel® Quark CoreThe pseudo LRU mechanism works

Strany 24 - 3.3.2 Segment Register Usage

Intel® Quark Core—ContentsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201312 Order Number: 329679-001US9 Base Architecture Registers ...

Strany 25 - 3.5 Addressing Modes

Intel® Quark Core—On-Chip CacheIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013120 Order Number: 329679-001USThe state of the PCD bit in the

Strany 26 - Example: ADD EAX, TABLE[ESI]

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 121On-Chip Cache—Intel® Quark CoreFigure 52. Page Cacheability7.6

Strany 27 - A5159-01

Intel® Quark Core—On-Chip CacheIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013122 Order Number: 329679-001US7.7 Cache FlushingThe on-chip c

Strany 28 - 3.6 Data Types

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 123On-Chip Cache—Intel® Quark CoreSnoop cycles with invalidation

Strany 29 - 3.6.1.2 Signed Data Types

Intel® Quark Core—On-Chip CacheIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013124 Order Number: 329679-001USWith the modified MESI protocol

Strany 30 - 3.6.1.5 String Data Types

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 125On-Chip Cache—Intel® Quark CoreNote that even though memory wr

Strany 31 - 3.6.1.6 ASCII Data Types

Intel® Quark Core—On-Chip CacheIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013126 Order Number: 329679-001USA software mechanism to determi

Strany 32 - 3.6.1.7 Pointer Data Types

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 127System Management Mode (SMM) Architectures—Intel® Quark Core8.

Strany 33 - 3.7 Interrupts

Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013128 Order Number: 329679-001USSM

Strany 34 - 3.7.3 Maskable Interrupt

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 129System Management Mode (SMM) Architectures—Intel® Quark CoreTh

Strany 35 - 3.7.4 Non-Maskable Interrupt

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 13Contents—Intel® Quark Core61 I/O Instruction Restart...

Strany 36 - 3.7.5 Software Interrupts

Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013130 Order Number: 329679-001USTh

Strany 37 - 3.7.7 Instruction Restart

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 131System Management Mode (SMM) Architectures—Intel® Quark CoreTh

Strany 38 - 3.7.8 Double Fault

Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013132 Order Number: 329679-001USFi

Strany 39 - 4.2 Floating-Point Registers

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 133System Management Mode (SMM) Architectures—Intel® Quark Core8.

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Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013134 Order Number: 329679-001USAu

Strany 41 - 4.3.3 Flags Register

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 135System Management Mode (SMM) Architectures—Intel® Quark CoreFi

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Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013136 Order Number: 329679-001USWh

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 137System Management Mode (SMM) Architectures—Intel® Quark CoreTh

Strany 44 - 4.3.4 Segment Registers

Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013138 Order Number: 329679-001US8.

Strany 45 - 4.4 System-Level Registers

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 139System Management Mode (SMM) Architectures—Intel® Quark Corein

Strany 46 - 4.4.1 Control Registers

Intel® Quark Core—ContentsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201314 Order Number: 329679-001US113 Snoop Cycle Invalidating a Modifi

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Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013140 Order Number: 329679-001USIf

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 141System Management Mode (SMM) Architectures—Intel® Quark CoreTo

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Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013142 Order Number: 329679-001USIf

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 143System Management Mode (SMM) Architectures—Intel® Quark CoreFi

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Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013144 Order Number: 329679-001USFi

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 145System Management Mode (SMM) Architectures—Intel® Quark CoreIf

Strany 53 - A5150-01

Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013146 Order Number: 329679-001US8.

Strany 54 - 4.5.2 Floating-Point Tag Word

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 147System Management Mode (SMM) Architectures—Intel® Quark Corele

Strany 55 - A5152-01

Intel® Quark Core—System Management Mode (SMM) ArchitecturesIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013148 Order Number: 329679-001US•

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 149Hardware Interface—Intel® Quark Core9.0 Hardware Interface9.1

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 15Contents—Intel® Quark Core28 Descriptor Types Used for Control

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Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013150 Order Number: 329679-001US9.2 Signal Descriptions9.2

Strany 59 - IP Offset

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 151Hardware Interface—Intel® Quark Coreaddress space (00000000H t

Strany 60 - 16-Bit Protected Mode Format

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013152 Order Number: 329679-001USindicated by the byte enab

Strany 61 - 4.5.5 FPU Control Word

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 153Hardware Interface—Intel® Quark Core9.2.5.3 Pseudo-Lock Output

Strany 62 - 4.7 Register Accessibility

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013154 Order Number: 329679-001USRDY# is active low, and is

Strany 63 - 4.7.1 FPU Register Usage

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 155Hardware Interface—Intel® Quark Core9.2.8.2 Soft Reset Input (

Strany 64 - 4.9 Intel

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013156 Order Number: 329679-001US9.2.8.6 Non-maskable Inter

Strany 65 - 5.0 Real Mode Architecture

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 157Hardware Interface—Intel® Quark Coreperforming a code fetch, a

Strany 66 - 5.3 Reserved Locations

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013158 Order Number: 329679-001US9.2.10.1 Address Hold Requ

Strany 67 - 5.5 Shutdown and Halt

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 159Hardware Interface—Intel® Quark CoreFLUSH# also determines whe

Strany 68 - 6.1 Addressing Mechanism

Intel® Quark Core—ContentsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201316 Order Number: 329679-001US78 Encoding of reg Field when the (w)

Strany 69 - 6.2 Segmentation

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013160 Order Number: 329679-001US1. The stack fault, invali

Strany 70 - 6.2.3 Descriptor Tables

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 161Hardware Interface—Intel® Quark CoreBS16# and BS8# are active

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Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013162 Order Number: 329679-001US9.2.17.2 Cache Flush (FLUS

Strany 72 - 6.2.4.2 Intel

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 163Hardware Interface—Intel® Quark Core9.2.17.4 Soft Reset (SRESE

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Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013164 Order Number: 329679-001US9.2.17.6 Write-Back/Write-

Strany 74 - 1Writeable (W)

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 165Hardware Interface—Intel® Quark CoreIn addition to using TCK a

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Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013166 Order Number: 329679-001US9.3.1 Interrupt LogicThe I

Strany 76 - Offset 31...16 P

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 167Hardware Interface—Intel® Quark CoreThe SMI# input must be hel

Strany 77 - 6.2.4.7 Selector Fields

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013168 Order Number: 329679-001USWrites are driven onto the

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 169Hardware Interface—Intel® Quark Core9.4.1 Write Buffers and I/

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 17About this Manual—Intel® Quark Core1.0 About this ManualThis ma

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Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013170 Order Number: 329679-001US9.5.1 Floating-Point Regis

Strany 81 - 6.3 Protection

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 171Hardware Interface—Intel® Quark Core9.5.2 Pin State During Res

Strany 82 - 6.3.3.1 Task Privilege

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013172 Order Number: 329679-001USFigure 72. Pin States Duri

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 173Hardware Interface—Intel® Quark Core9.5.2.1 Controlling the CL

Strany 84 - Figure 36. Intel

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013174 Order Number: 329679-001US7:0 depend on whether or n

Strany 85 - 6.3.3.5 Descriptor Access

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 175Hardware Interface—Intel® Quark CoreM/IO# = 0, D/C# = 0, W/R#

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Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013176 Order Number: 329679-001US9.6.3 Write-Back Enhanced

Strany 87 - 6.3.5 Call Gates

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 177Hardware Interface—Intel® Quark CoreThe Write-Back Enhanced In

Strany 88 - 6.3.6 Task Switching

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013178 Order Number: 329679-001USare not recognized until o

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 179Hardware Interface—Intel® Quark Core9.6.4.3 Stop Clock StateSt

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Intel® Quark Core—About this ManualIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201318 Order Number: 329679-001US1.2 Notation ConventionsThe

Strany 91 - 6.4.2.1 Page Mechanism

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013180 Order Number: 329679-001USA FLUSH# event during the

Strany 92 - 6.4.2.4 Page Tables

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 181Hardware Interface—Intel® Quark CoreFigure 76. Write-Back Enha

Strany 93 - 6.4.3.1 PDPTE Registers

Intel® Quark Core—Hardware InterfaceIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013182 Order Number: 329679-001US• The processor latches an

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 183Hardware Interface—Intel® Quark Corein this state, the FLUSH#

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013184 Order Number: 329679-001US10.0 Bus OperationWhen the inte

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 185Bus Operation—Intel® Quark CoreFigure 77. Physical Memory and

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013186 Order Number: 329679-001USFigure 78. Physical Memory and

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 187Bus Operation—Intel® Quark CoreThe external system must contai

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013188 Order Number: 329679-001USIn 32-bit physical memories, su

Strany 100 - 6.4.5 Access Rights

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 189Bus Operation—Intel® Quark CoreTable 64. Generating A1, BHE# a

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 19About this Manual—Intel® Quark CoreRegister Bits When the text

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013190 Order Number: 329679-001USCombinations of BE[3:0]# that n

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 191Bus Operation—Intel® Quark CoreFigure 82. Data Bus Interface t

Strany 104 - 6.4.9 Page-Fault Exceptions

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013192 Order Number: 329679-001US10.1.5 Operand AlignmentPhysica

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 193Bus Operation—Intel® Quark CoreIn the unaligned transfer descr

Strany 106 - 6.4.10 Paging Operation

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013194 Order Number: 329679-001USFigure 84. Single Intel® Quark

Strany 107 - 6.5 Virtual 8086 Environment

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 195Bus Operation—Intel® Quark CoreFigure 85. Single Intel® Quark

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013196 Order Number: 329679-001USThe Intel® Quark SoC X1000 Core

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 197Bus Operation—Intel® Quark CoreFigure 86. Basic 2-2 Bus CycleT

Strany 110 - 6.5.5 Interrupt Handling

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013198 Order Number: 329679-001USFigure 87. Basic 3-3 Bus CycleT

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 199Bus Operation—Intel® Quark CoreBurst cycles begin with the Int

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Intel® Quark SoC X1000 CoreDeveloper’s Manual October 20132 Order Number: 329679-001USLegal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVI

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Intel® Quark Core—About this ManualIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201320 Order Number: 329679-001US1.4 Related DocumentsThe fol

Strany 114 - 7.0 On-Chip Cache

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013200 Order Number: 329679-001US10.3.2.3 Non-Cacheable, Non-Bur

Strany 115 - Quark SoC X1000 Core Cache

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 201Bus Operation—Intel® Quark CoreFigure 89. Non-Cacheable Burst

Strany 116 - 7.2 Cache Control

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013202 Order Number: 329679-001USconditions 1–3 in the above lis

Strany 117 - 7.3 Cache Line Fills

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 203Bus Operation—Intel® Quark CoreFigure 90. Non-Burst, Cacheable

Strany 118 - 7.5 Cache Replacement

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013204 Order Number: 329679-001USFigure 91. Burst Cacheable Cycl

Strany 119 - 7.6 Page Cacheability

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 205Bus Operation—Intel® Quark CoreFigure 92. Effect of Changing K

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013206 Order Number: 329679-001USFigure 93. Slow Burst Cycle10.3

Strany 121 - Processor Page Cacheability

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 207Bus Operation—Intel® Quark CoreFigure 94. Burst Cycle Showing

Strany 122 - 7.7 Cache Flushing

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013208 Order Number: 329679-001USFigure 95. Interrupted Burst Cy

Strany 123 - Back Cache Architecture

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 209Bus Operation—Intel® Quark CoreFigure 96. Interrupted Burst Cy

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 21Intel® Quark SoC X1000 Core Overview—Intel® Quark Core2.0 Intel

Strany 125 - Enhanced Intel

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013210 Order Number: 329679-001USFigure 97. 8-Bit Bus Size Cycle

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 211Bus Operation—Intel® Quark CoreFigure 98. Burst Write as a Res

Strany 127 - 8.2 Terminology

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013212 Order Number: 329679-001USFigure 99. Locked Bus Cycle10.3

Strany 128 - A5237-01

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 213Bus Operation—Intel® Quark CorePLOCK# can change several times

Strany 129 - 8.3.2 SMI# Active (SMIACT#)

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013214 Order Number: 329679-001USFigure 101. Fast Internal Cache

Strany 130 - A5232-01

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 215Bus Operation—Intel® Quark Core10.3.8.1 Rate of Invalidate Cyc

Strany 131 - 8.3.3.1 SMRAM State Save Map

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013216 Order Number: 329679-001USFigure 103. System with Second-

Strany 132 - Register Writeable?

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 217Bus Operation—Intel® Quark CoreFigure 104. Cache Invalidation

Strany 133 - 8.3.4 Exit From SMM

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013218 Order Number: 329679-001USFigure 105. HOLD/HLDA CyclesNot

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 219Bus Operation—Intel® Quark CoreFigure 106. HOLD Request Acknow

Strany 135 - 8.4.2 Processor Environment

Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201322 Order Number: 329679-001US3.0 Architectural Overv

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013220 Order Number: 329679-001USFigure 107. Interrupt Acknowled

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 221Bus Operation—Intel® Quark Core10.3.11.2 Shutdown Indication C

Strany 138 - 8.5 SMM Features

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013222 Order Number: 329679-001US10.3.12 Bus Cycle RestartIn a m

Strany 139 - 8.5.3 I/O Instruction Restart

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 223Bus Operation—Intel® Quark CoreFigure 110. Restarted Write Cyc

Strany 140 - 8.5.4 SMM Base Relocation

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013224 Order Number: 329679-001US10.3.13 Bus StatesA bus state d

Strany 141 - 8.6.1 SMRAM Interface

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 225Bus Operation—Intel® Quark Core10.3.14 Floating-Point Error Ha

Strany 142 - 8.6.2 Cache Flushes

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013226 Order Number: 329679-001USIn systems with user-defined er

Strany 143 - A5238-01

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 227Bus Operation—Intel® Quark Core2. Four signals: INV, WB/WT#, H

Strany 144 - Quark SoC X1000 Core System

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013228 Order Number: 329679-001UScacheable by either CACHE# or K

Strany 145 - A5240-01

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 229Bus Operation—Intel® Quark CoreX1000 Core invalidates the line

Strany 146 - 8.6.2.2 Snoop During SMM

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 23Architectural Overview—Intel® Quark CoreIn addition to these ba

Strany 147 - 8.7.1 SMM Code Considerations

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013230 Order Number: 329679-001US10.4.3.2 Snoop under AHOLDSnoop

Strany 148 - 8.7.3 Halt During SMM

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 231Bus Operation—Intel® Quark CoreFigure 113. Snoop Cycle Invalid

Strany 149 - 9.0 Hardware Interface

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013232 Order Number: 329679-001USIn Figure 114, the snoop to an

Strany 150 - 9.2 Signal Descriptions

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 233Bus Operation—Intel® Quark Core10.4.3.2.2 AHOLD Snoop Overlayi

Strany 151 - 9.2.4 Parity

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013234 Order Number: 329679-001US3. If the snoop occurs when INV

Strany 152 - 9.2.5 Bus Cycle Definition

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 235Bus Operation—Intel® Quark CoreIf there is a snoop hit to a di

Strany 153 - 9.2.6 Bus Control

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013236 Order Number: 329679-001USFigure 117. Snoop under BOFF# d

Strany 154 - 9.2.8.1 Reset Input (RESET)

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 237Bus Operation—Intel® Quark Core10.4.3.4.2 Snoop under BOFF# du

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013238 Order Number: 329679-001US10.4.3.5.1 Snoop under HOLD dur

Strany 156 - 9.2.9 Bus Arbitration Signals

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 239Bus Operation—Intel® Quark CoreFigure 120. Snoop using HOLD du

Strany 157 - 9.2.9.4 Backoff Input (BOFF#)

Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201324 Order Number: 329679-001USFigure 2. Address Trans

Strany 158 - 9.2.11 Cache Control

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013240 Order Number: 329679-001USto the system that the processo

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 241Bus Operation—Intel® Quark Core10.4.4.1 Snoop/Lock CollisionIf

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Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013242 Order Number: 329679-001USIf the processor is in Standard

Strany 161 - Other Enhanced Bus Features

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 243Bus Operation—Intel® Quark CoreFigure 124. Snoop under AHOLD O

Strany 162 - 9.2.17.2 Cache Flush (FLUSH#)

Intel® Quark Core—Bus OperationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013244 Order Number: 329679-001USFigure 125. Snoop under HOLD Ov

Strany 163 - 9.2.17.4 Soft Reset (SRESET)

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 245Bus Operation—Intel® Quark CoreFigure 126. Snoop under BOFF# O

Strany 164 - 9.2.18.1 Test Clock (TCK)

Intel® Quark Core—Debugging SupportIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013246 Order Number: 329679-001US11.0 Debugging SupportThe I

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 247Debugging Support—Intel® Quark Core11.3.1 Linear Address Break

Strany 166 - 9.3.3 SMI# Logic

Intel® Quark Core—Debugging SupportIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013248 Order Number: 329679-001USRWi (memory access qualifie

Strany 167 - 9.4 Write Buffers

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 249Debugging Support—Intel® Quark CoreNote that instruction execu

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 25Architectural Overview—Intel® Quark Core3.4 I/O SpaceThe Intel®

Strany 169 - 9.5 Reset and Initialization

Intel® Quark Core—Debugging SupportIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013250 Order Number: 329679-001USGi and Li (breakpoint enabl

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 251Debugging Support—Intel® Quark CoreBD (debug fault due to atte

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013252 Order Number: 329679-001US12.0 Instruction Set

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 253Instruction Set Summary—Intel® Quark Core12.1.1 Floating-Point

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 255Instruction Set Summary—Intel® Quark Core12.2.3 Encoding of In

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 257Instruction Set Summary—Intel® Quark Core12.2.3.4 Encoding of

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013258 Order Number: 329679-001USTable 81. Encoding of

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 259Instruction Set Summary—Intel® Quark CoreTable 82. Encoding of

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Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201326 Order Number: 329679-001US3.5.2 Register and Imme

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013260 Order Number: 329679-001US12.2.3.5 Encoding of

Strany 181 - 9.6.5.2 Stop Grant State

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 261Instruction Set Summary—Intel® Quark Core12.2.3.6 Encoding of

Strany 182 - 9.6.5.3 Stop Clock State

Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013262 Order Number: 329679-001US12.2.4 Encoding of Fl

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 263Instruction Set Summary—Intel® Quark Core12.2.5 Intel® Quark S

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013264 Order Number: 329679-001USIn 64-bit mode, defau

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 265Instruction Set Summary—Intel® Quark CoreThis instruction must

Strany 186 - BHE# BLE#

Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013266 Order Number: 329679-001USWhen the destination

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 267Instruction Set Summary—Intel® Quark CoreTable 89. Clock Count

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013268 Order Number: 329679-001USLEA = Load EA to Regi

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 269Instruction Set Summary—Intel® Quark CoreTEST = Logical Compar

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 27Architectural Overview—Intel® Quark CoreBased Scaled Index Mode

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013270 Order Number: 329679-001USIMUL = Integer Multip

Strany 192 - 10.1.5 Operand Alignment

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 271Instruction Set Summary—Intel® Quark CoreCWD = Convert Word to

Strany 193 - 10.2 Bus Arbitration Logic

Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013272 Order Number: 329679-001USCONTROL TRANSFER (wit

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 273Instruction Set Summary—Intel® Quark CoreRET = Return from CAL

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013274 Order Number: 329679-001USRET = Return from CAL

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 275Instruction Set Summary—Intel® Quark CoreSTRING INSTRUCTIONSCM

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013276 Order Number: 329679-001USSTD = Set Direction F

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 277Instruction Set Summary—Intel® Quark CoreINVD = Invalidate Dat

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013278 Order Number: 329679-001USLTR = Load Task Regis

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 279Instruction Set Summary—Intel® Quark CoreRSM = Exit System Ma

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Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201328 Order Number: 329679-001US3.5.4 Differences Betwe

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013280 Order Number: 329679-001USProtected ModeInterru

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 281Instruction Set Summary—Intel® Quark Core1. Assuming that the

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013282 Order Number: 329679-001USVariable Port 1110 11

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 283Instruction Set Summary—Intel® Quark CoreTable 94. Floating-Po

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013284 Order Number: 329679-001USFXCH = Exchange ST(0)

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 285Instruction Set Summary—Intel® Quark CoreCONSTANTSFLDZ = Load

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013286 Order Number: 329679-001USFSUB = Subtract Real

Strany 209 - 10.3.5 8- and 16-Bit Cycles

Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 287Instruction Set Summary—Intel® Quark CoreFDIV = Divide ST(0) b

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Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013288 Order Number: 329679-001USFISUBR = Integer Subt

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 289Instruction Set Summary—Intel® Quark CoreFABS = Absolute value

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 29Architectural Overview—Intel® Quark Core3.6.1.1 Unsigned Data T

Strany 213 - 10.3.8 Invalidate Cycles

Intel® Quark Core—Instruction Set SummaryIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013290 Order Number: 329679-001USFCLEX = Clear excepti

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 291Signal Descriptions—Intel® Quark CoreAppendix A Signal Descrip

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Intel® Quark Core—Signal DescriptionsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013292 Order Number: 329679-001USLOCK# OThe Bus Lock pin i

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 293Signal Descriptions—Intel® Quark CoreSRESET IThe Soft Reset pi

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Intel® Quark Core—Signal DescriptionsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013294 Order Number: 329679-001USFLUSH# IThe Cache Flush i

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 295Signal Descriptions—Intel® Quark CoreWRITE-BACK ENHANCED Intel

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Intel® Quark Core—TestabilityIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013296 Order Number: 329679-001USAppendix B TestabilityThis append

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 297Testability—Intel® Quark CoreCache Data Test Register: TR3The

Strany 221 - ADDR Data

Intel® Quark Core—TestabilityIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013298 Order Number: 329679-001USto TR3 initiates the write to the

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 299Testability—Intel® Quark Corewill be corrupted. This is becaus

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 3Revision History—Intel® Quark CoreRevision HistoryDate Revision

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Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201330 Order Number: 329679-001US8-bit Integer: Signed 8

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Intel® Quark Core—TestabilityIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013300 Order Number: 329679-001USFigure 130. TR4 Definition for St

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 301Testability—Intel® Quark CoreB.2.2 TLB Test Registers TR6 and

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Intel® Quark Core—TestabilityIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013302 Order Number: 329679-001USFigure 133. TLB Test RegistersThe

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 303Testability—Intel® Quark CoreB.2.2.2 Data Test Register: TR7TR

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Intel® Quark Core—TestabilityIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013304 Order Number: 329679-001USTR6 must be written to initiate t

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 305Testability—Intel® Quark CoreB.3.1.1 Test-Logic-Reset StateIn

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Intel® Quark Core—TestabilityIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013306 Order Number: 329679-001USB.3.1.4 Capture-DR StateIn this s

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 307Testability—Intel® Quark CoreB.3.1.9 Update-DR StateThe JTAG r

Strany 233 - Fill Cont

Intel® Quark Core—TestabilityIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013308 Order Number: 329679-001USThe test data register selected b

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 309Feature Determination—Intel® Quark CoreAppendix C Feature Dete

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 31Architectural Overview—Intel® Quark Core3.6.1.6 ASCII Data Type

Strany 236 - 40 04C80C8

Intel® Quark Core—Feature DeterminationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 2013310 Order Number: 329679-001USThe Intel® Quark SoC X1

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 311Feature Determination—Intel® Quark CoreRefer to the Intel appl

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Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201332 Order Number: 329679-001USFigure 6. String and AS

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 33Architectural Overview—Intel® Quark Core3.6.2 Little Endian vs.

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Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201334 Order Number: 329679-001USExceptions are classifi

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 35Architectural Overview—Intel® Quark CoreThe IF bit in the EFLAG

Strany 242 - 10.4.6 Pseudo Locked Cycles

Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201336 Order Number: 329679-001USWhile executing the NMI

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 37Architectural Overview—Intel® Quark CoreAs the Intel® Quark SoC

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Intel® Quark Core—Architectural OverviewIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201338 Order Number: 329679-001US3.7.8 Double FaultA Dou

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 39System Register Organization—Intel® Quark Core4.0 System Regist

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Intel® Quark Core—ContentsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 20134 Order Number: 329679-001USContents1.0 About this Manual...

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201340 Order Number: 329679-001USNote: In register

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 41System Register Organization—Intel® Quark CoreThe least signifi

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201342 Order Number: 329679-001USID (Identificatio

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 43System Register Organization—Intel® Quark CoreX1000 Core does n

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201344 Order Number: 329679-001USIF (INTR Enable F

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 45System Register Organization—Intel® Quark CoreFigure 11. Intel®

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201346 Order Number: 329679-001USFigure 12. System

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 47System Register Organization—Intel® Quark Core4.4.1.1 Control R

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201348 Order Number: 329679-001USThe low-order 16

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 49System Register Organization—Intel® Quark Corereach the externa

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 5Contents—Intel® Quark Core4.4.1.1 Control Register 0 (CR0)...

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201350 Order Number: 329679-001USTS (Task Switch,

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201352 Order Number: 329679-001USinstructions allo

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 53System Register Organization—Intel® Quark Core4.5 Floating-Poin

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201354 Order Number: 329679-001US4.5.2 Floating-Po

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 55System Register Organization—Intel® Quark CoreFigure 17. Floati

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201356 Order Number: 329679-001USTable 14. Conditi

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 57System Register Organization—Intel® Quark CoreBit 7 is the erro

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201358 Order Number: 329679-001USSection 4.5.4.Not

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 59System Register Organization—Intel® Quark CoreFigure 18. Protec

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Intel® Quark Core—ContentsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 20136 Order Number: 329679-001US6.3.5 Call Gates...

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 61System Register Organization—Intel® Quark CoreFigure 22. FPU Co

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201362 Order Number: 329679-001USaffects only the

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 63System Register Organization—Intel® Quark Core4.7.1 FPU Registe

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Intel® Quark Core—System Register OrganizationIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201364 Order Number: 329679-001US• Do not depend o

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 65Real Mode Architecture—Intel® Quark Core5.0 Real Mode Architect

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Intel® Quark Core—Real Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201366 Order Number: 329679-001US5.2 Memory AddressingIn

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 67Real Mode Architecture—Intel® Quark Core5.4 InterruptsMany of t

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201368 Order Number: 329679-001US6.0 Protected Mode

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 69Protected Mode Architecture—Intel® Quark Core6.2 Segmentation6.

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 7Contents—Intel® Quark Core8.1 SMM Overview...

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201370 Order Number: 329679-001US6.2.2 TerminologyT

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 71Protected Mode Architecture—Intel® Quark Core6.2.3.2 Global Des

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201372 Order Number: 329679-001USFigure 27. Interru

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 73Protected Mode Architecture—Intel® Quark Coregranularity is unr

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201374 Order Number: 329679-001USSegments identifie

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 75Protected Mode Architecture—Intel® Quark CoreFigure 29. System

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201376 Order Number: 329679-001USparameters are to

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 77Protected Mode Architecture—Intel® Quark Core6.2.4.7 Selector F

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201378 Order Number: 329679-001USFigure 31. Example

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 79Protected Mode Architecture—Intel® Quark CoreWhen operating in

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Intel® Quark Core—ContentsIntel® Quark SoC X1000 CoreDeveloper’s Manual October 20138 Order Number: 329679-001US9.2.8.1 Reset Input (RESET)...

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Intel® Quark Core—Protected Mode ArchitectureIntel® Quark SoC X1000 CoreDeveloper’s Manual October 201380 Order Number: 329679-001USFigure 33. Segment

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Intel® Quark SoC X1000 CoreOctober 2013 Developer’s ManualOrder Number: 329679-001US 81Protected Mode Architecture—Intel® Quark Core6.3 Protection6.3.

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