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Intel
®
Pentium
®
4 Processor
Supporting Hyper-Threading
Technology
1
Datasheet
3.80F GHz, 3.60F GHz, 3.40F GHz, 3.20F GHz on 90 nm
Process in 775-land LGA Package and supporting Intel
®
Extended Memory 64 Technology
2
for single processor
servers and workstations
Document Number: 303128-004
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Strany 1 - Technology

Intel® Pentium® 4 Processor Supporting Hyper-Threading Technology1Datasheet3.80F GHz, 3.60F GHz, 3.40F GHz, 3.20F GHz on 90 nm Process in 775-land LGA

Strany 2 - Contents

10 DatasheetIntroductionnon-executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This

Strany 3

Datasheet 11Introductionany I/Os biased, or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packag

Strany 4 - 4 Datasheet

12 DatasheetIntroduction

Strany 5 - Datasheet 5

Datasheet 13Electrical Specifications2 Electrical Specifications2.1 FSB and GTLREFMost processor FSB signals use Gunning Transceiver Logic (GTL+) sig

Strany 6 - 6 Datasheet

14 DatasheetElectrical Specifications2.3.1 VCC DecouplingRegulator solutions need to provide bulk capacitance with a low Effective Series Resistance

Strany 7 - Revision History

Datasheet 15Electrical Specifications2.4 Voltage IdentificationThe VID specification for the Pentium 4 processor in the 775-land package is supported

Strany 8 - Hyper-Threading Technology

16 DatasheetElectrical SpecificationsTable 2-2. Voltage Identification DefinitionVID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID

Strany 9 - 1 Introduction

Datasheet 17Electrical Specifications2.4.1 Phase Lock Loop (PLL) Power and FilterVCCA and VCCIOPLL are power sources required by the PLL clock genera

Strany 10 - 1.1 Terminology

18 DatasheetElectrical Specifications2.5 Reserved, Unused, FC and TESTHI SignalsAll RESERVED signals must remain unconnected. Connection of these sig

Strany 11 - 1.2 References

Datasheet 19Electrical Specifications2.6 FSB Signal GroupsThe FSB signals have been combined into groups by buffer type. GTL+ input signals have diff

Strany 12 - Introduction

2 Datasheet ContentsINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERW

Strany 13 - 2 Electrical Specifications

20 DatasheetElectrical SpecificationsNOTES:1. Refer to Section 4.2 for signal descriptions.2. In processor systems where there is no debug port imple

Strany 14 - Decoupling

Datasheet 21Electrical Specifications2.8 Test Access Port (TAP) ConnectionDue to the voltage levels supported by other components in the Test Access

Strany 15 - 2.4 Voltage Identification

22 DatasheetElectrical Specifications2.10 Absolute Maximum and Minimum RatingsTable 2-7 specifies absolute maximum and minimum ratings. Within functi

Strany 16 - Electrical Specifications

Datasheet 23Electrical SpecificationsTable 2-8. Voltage and Current SpecificationsSymbol Parameter Min Typ Max Unit Notes1NOTES:1. Unless otherwise n

Strany 17 - Datasheet 17

24 DatasheetElectrical Specifications6. 775_VR_CONFIG_04A and 775_VR_CONFIG_04B refer to voltage regulator configurations that are de-fined in the Vo

Strany 18 - 18 Datasheet

Datasheet 25Electrical SpecificationsNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sh

Strany 19 - 2.6 FSB Signal Groups

26 DatasheetElectrical Specifications45 -0.059 -0.080 -0.10150 -0.065 -0.087 -0.10855 -0.072 -0.093 -0.11560 -0.078 -0.100 -0.12265 -0.085 -0.107 -0.

Strany 20 - 2.7 GTL+ Asynchronous Signals

Datasheet 27Electrical SpecificationsNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sh

Strany 21 - Datasheet 21

28 DatasheetElectrical Specifications6. The VTT referred to in these specifications refers to instantaneous VTT.7. All outputs are open drain.8. The

Strany 22 - 22 Datasheet

Datasheet 29Electrical Specifications2.12 VCC Overshoot SpecificationThe Pentium 4 processor in the 775-land package can tolerate short transient ove

Strany 23

Datasheet 3ContentsContents1 Introduction...

Strany 24 - Table 2-9. V

30 DatasheetElectrical SpecificationsNOTES:1. VOS is measured overshoot voltage.2. TOS is measured time duration above VID.2.12.1 Die Voltage Validat

Strany 25 - Datasheet 25

Datasheet 31Electrical Specifications§Table 2-18. GTL+ Bus Voltage DefinitionsSymbol Parameter Min Typ Max Units Notes1NOTES:1. Unless otherwise note

Strany 26 - Table 2-10. V

32 DatasheetElectrical Specifications

Strany 27 - Figure 2-3. V

Datasheet 33Package Mechanical Specifications3 Package Mechanical Specifications3.1 Package Mechanical SpecificationsThe Pentium 4 processor in the 7

Strany 28

34 DatasheetPackage Mechanical SpecificationsFigure 3-2. Processor Package Drawing 1

Strany 29 - Overshoot Specification

Datasheet 35Package Mechanical SpecificationsFigure 3-3. Processor Package Drawing 2

Strany 30 - 2.13 GTL+ FSB Specifications

36 DatasheetPackage Mechanical SpecificationsFigure 3-4. Processor Package Drawing 3

Strany 31

Datasheet 37Package Mechanical Specifications3.1.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that defin

Strany 32

38 DatasheetPackage Mechanical Specifications3.1.5 Package Insertion SpecificationsThe Pentium 4 processor in the 775-land package can be inserted in

Strany 33 - 3 Package Mechanical

Datasheet 39Package Mechanical Specifications3.1.9 Processor Land CoordinatesFigure 3-6 shows the top view of the processor land coordinates. The coo

Strany 34 - 34 Datasheet

4 Datasheet Contents5.2.2 Thermal Monitor 2...785.2.3

Strany 35 - Datasheet 35

40 DatasheetPackage Mechanical Specifications

Strany 36 - 36 Datasheet

41 DatasheetLand Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal

Strany 37 - Datasheet 37

42 DatasheetLand Listing and Signal DescriptionsFigure 4-1. Landout Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVC

Strany 38 - 3.1.8 Processor Markings

Datasheet 43Land Listing and Signal DescriptionsFigure 4-2. Landout Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VS

Strany 39 - Top View

Land Listing and Signal Descriptions44 DatasheetTable 4-1. Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA3# L5 Source Synch

Strany 40 - 40 Datasheet

Land Listing and Signal Descriptions Datasheet 45D23# F11 Source Synch Input/OutputD24# F12 Source Synch Input/OutputD25# D13 Source Synch Input/Outpu

Strany 41 - 4 Land Listing and Signal

Land Listing and Signal Descriptions46 DatasheetITP_CLK1 AJ3 TAP InputLINT0 K1 Asynch GTL+ InputLINT1 L1 Asynch GTL+ InputLL_ID0 V2 Power/Other Outpu

Strany 42 - 42 Datasheet

Land Listing and Signal Descriptions Datasheet 47VCC AC26 Power/Other VCC AC27 Power/Other VCC AC28 Power/Other VCC AC29 Power/Other VCC AC30 Powe

Strany 43 - Datasheet 43

Land Listing and Signal Descriptions48 DatasheetVCC AK12 Power/Other VCC AK14 Power/Other VCC AK15 Power/Other VCC AK18 Power/Other VCC AK19 Powe

Strany 44 - Assignments

Land Listing and Signal Descriptions Datasheet 49VCC K29 Power/Other VCC K30 Power/Other VCC K8 Power/Other VCC L8 Power/Other VCC M23 Power/Other

Strany 45

Datasheet 5ContentsFigures2-1 Phase Lock Loop (PLL) Filter Requirements...

Strany 46

Land Listing and Signal Descriptions50 DatasheetVSS AA24 Power/Other VSS AA25 Power/Other VSS AA26 Power/Other VSS AA27 Power/Other VSS AA28 Powe

Strany 47

Land Listing and Signal Descriptions Datasheet 51VSS AJ23 Power/Other VSS AJ24 Power/Other VSS AJ27 Power/Other VSS AJ28 Power/Other VSS AJ29 Powe

Strany 48

Land Listing and Signal Descriptions52 DatasheetVSS E11 Power/Other VSS E14 Power/Other VSS E17 Power/Other VSS E2 Power/Other VSS E20 Power/Othe

Strany 49

Land Listing and Signal Descriptions Datasheet 53VSS R30 Power/Other VSS R5 Power/Other VSS R7 Power/Other VSS T3 Power/Other VSS T6 Power/Other

Strany 50

Land Listing and Signal Descriptions54 DatasheetTable 4-2. Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA2 VSS Power/Other A3

Strany 51

Land Listing and Signal Descriptions Datasheet 55C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power/Other C27 VTT Power/Other C28 VTT Power/Oth

Strany 52

Land Listing and Signal Descriptions56 DatasheetF19 VSS Power/Other F20 D41# Source Synch Input/OutputF21 D43# Source Synch Input/OutputF22 VSS Powe

Strany 53

Land Listing and Signal Descriptions Datasheet 57J13 VCC Power/Other J14 VCC Power/Other J15 VCC Power/Other J16 DP0# Common Clock Input/OutputJ17

Strany 54 - 54 Datasheet

Land Listing and Signal Descriptions58 DatasheetP1 TESTHI11 Power/Other InputP2 SMI# Asynch GTL+ InputP3 INIT# Asynch GTL+ InputP4 VSS Power/Other P

Strany 55 - Datasheet 55

Land Listing and Signal Descriptions Datasheet 59W3 TESTHI1 Power/Other InputW4 VSS Power/Other W5 A16# Source Synch Input/OutputW6 A18# Source Synch

Strany 56 - 56 Datasheet

6 Datasheet ContentsTables1-1 References ...

Strany 57 - Datasheet 57

Land Listing and Signal Descriptions60 DatasheetAD6 A22# Source Synch Input/OutputAD7 VSS Power/Other AD8 VCC Power/Other AD23 VCC Power/Other AD2

Strany 58 - 58 Datasheet

Land Listing and Signal Descriptions Datasheet 61AG12 VCC Power/Other AG13 VSS Power/Other AG14 VCC Power/Other AG15 VCC Power/Other AG16 VSS Powe

Strany 59 - Datasheet 59

Land Listing and Signal Descriptions62 DatasheetAK4 VID4 Power/Other OutputAK5 VSS Power/Other AK6 RESERVEDAK7 VSS Power/Other AK8 VCC Power/Other

Strany 60 - 60 Datasheet

Land Listing and Signal Descriptions Datasheet 63AM27 VSS Power/Other AM28 VSS Power/Other AM29 VCC Power/Other AM30 VCC Power/Other AN1 VSS Power

Strany 61 - Datasheet 61

64 DatasheetLand Listing and Signal Descriptions4.2 Alphabetical Signals ReferenceTable 4-3. Signal Description (Sheet 1 of 9)Name Type DescriptionA[

Strany 62 - 62 Datasheet

65 DatasheetLand Listing and Signal DescriptionsBINIT#Input/OutputBINIT# (Bus Initialization) may be observed and driven by all processor FSB agents

Strany 63 - Datasheet 63

66 DatasheetLand Listing and Signal DescriptionsD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path be

Strany 64 - 64 Datasheet

67 DatasheetLand Listing and Signal DescriptionsDRDY#Input/OutputDRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating

Strany 65 - 65 Datasheet

68 DatasheetLand Listing and Signal DescriptionsIGNNE# InputIGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric erro

Strany 66 - 66 Datasheet

69 DatasheetLand Listing and Signal DescriptionsPROCHOT#Input/OutputAs an output, PROCHOT# (Processor Hot) will go active when the processor temperat

Strany 67 - 67 Datasheet

Datasheet 7ContentsRevision HistoryRevision No. Description Date of Release-001 • Initial release August 2004-002• Added server support for Intel® E

Strany 68 - 68 Datasheet

70 DatasheetLand Listing and Signal DescriptionsSTPCLK# InputSTPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Gran

Strany 69 - 69 Datasheet

71 DatasheetLand Listing and Signal Descriptions§VID[5:0] OutputVID[5:0] (Voltage ID) signals are used to support automatic selection of power supply

Strany 70 - 70 Datasheet

72 DatasheetLand Listing and Signal Descriptions

Strany 71 - 71 Datasheet

Datasheet 73Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

Strany 72 - 72 Datasheet

74 DatasheetThermal Specifications and Design ConsiderationsThe case temperature is defined at the geometric top center of the processor IHS. Analysi

Strany 73 - 5 Thermal Specifications and

Datasheet 75Thermal Specifications and Design Considerations38 53.5 98 68.540 54.0 100 69.042 54.5 102 69.544 55.0 104 70.046 55.5 106 70.548 56.0 10

Strany 74 - 74 Datasheet

76 DatasheetThermal Specifications and Design Considerations6 45.9 50 58.28 46.4 52 58.810 47.0 54 59.312 47.6 56 59.914 48.1 58 60.416 48.7 60 61.01

Strany 75 - Datasheet 75

Datasheet 77Thermal Specifications and Design Considerations5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) are specified in Ta

Strany 76 - 76 Datasheet

78 DatasheetThermal Specifications and Design ConsiderationsWith a properly designed and characterized thermal solution, it is anticipated that the T

Strany 77 - Datasheet 77

Datasheet 79Thermal Specifications and Design ConsiderationsThe PROCHOT# signal is asserted when a high temperature situation is detected, regardless

Strany 78 - 5.2.2 Thermal Monitor 2

8 Datasheet ContentsIntel® Pentium® 4 Processor Supporting Hyper-Threading Technology1The Intel® Pentium® 4 processor family supporting Hyper-Threadi

Strany 79 - Datasheet 79

80 DatasheetThermal Specifications and Design Considerationswill be active when PROCHOT# is asserted. The processor can be configured to generate an

Strany 80 - and Fan Speed Reduction

Datasheet 81Thermal Specifications and Design Considerations5.2.7 Thermal DiodeThe processor incorporates an on-die thermal diode. A thermal sensor l

Strany 81 - 5.2.7 Thermal Diode

82 DatasheetThermal Specifications and Design Considerations

Strany 82 - 82 Datasheet

Datasheet 83Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The Pentium 4 processor

Strany 83 - 6 Features

84 DatasheetFeatures6.2.2 HALT and Enhanced HALT Powerdown StatesThe processor supports the HALT or Enhanced HALT powerdown state. The Enhanced HALT

Strany 84 - 6.2.2.1 HALT Powerdown State

Datasheet 85Features6.2.3 Stop-Grant StateWhen the STPCLK# signal is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after t

Strany 85 - Datasheet 85

86 DatasheetFeatures6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop StateThe Enhanced HALT Snoop State is used in conjunction with the new

Strany 86 - 86 Datasheet

Datasheet 87Boxed Processor Specifications7 Boxed Processor SpecificationsThe Pentium 4 processor on 90 nm process in the 775-land package will also

Strany 87 - Datasheet 87

88 DatasheetBoxed Processor Specifications7.1 Mechanical Specifications7.1.1 Boxed Processor Cooling Solution DimensionsThis section documents the me

Strany 88 - 7.1 Mechanical Specifications

Datasheet 89Boxed Processor Specifications7.1.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 450 gram

Strany 89 - 7.2 Electrical Requirements

Datasheet 9Introduction1 IntroductionThe Intel® Pentium® 4 processor on 90 nm process in the 775-land package is a follow on to the Pentium 4 process

Strany 90 - 90 Datasheet

90 DatasheetBoxed Processor SpecificationsThe fan heatsink outputs a SENSE signal that is an open-collector output that pulses at a rate of 2 pulses

Strany 91 - 7.3 Thermal Specifications

Datasheet 91Boxed Processor Specifications7.3 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution used

Strany 92 - 92 Datasheet

92 DatasheetBoxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)Figure 7-8. Boxed Process

Strany 93 - 7.3.2 Variable Speed Fan

Datasheet 93Boxed Processor Specifications7.3.2 Variable Speed FanIf the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherb

Strany 94 - 94 Datasheet

94 DatasheetBoxed Processor SpecificationsIf the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the moth

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