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Document Number: 316704-001 Intel® CoreTM 2 Duo processor and Mobile Intel® GME965 Express Chipset Development Kit User Manual June 2007

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About This Manual 10 316704-001 / Development Kit User’s Manual Term/Acronym Definition System Bus The System Bus is the microprocessor bus of

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About This Manual 316704-001 / Development Kit User’s Manual 11 Acronym Definition BIOS Basic Input/Output System CK-SSCD Spread Spectrum Diff

Strany 4 - Figures

About This Manual 12 316704-001 / Development Kit User’s Manual Acronym Definition LOM LAN on Motherboard LPC Low Pin Count LS Low-speed. Re

Strany 5 - Revision History

About This Manual 316704-001 / Development Kit User’s Manual 13 Acronym Definition VREG Voltage Regulator XDP eXtended Debug Port 1.4 Suppor

Strany 6 - 1 About This Manual

About This Manual 14 316704-001 / Development Kit User’s Manual Intel Literature Fulfilment Center P.O. Box 5937 Denver, Colorado 80217-9808 US

Strany 7 - Table 1. Text Conventions

Getting Started 316704-001 / Development Kit User’s Manual 15 2 Getting Started This chapter identifies the development kit’s key components,

Strany 8 - Table 2. Terms and Acronyms

Getting Started 16 316704-001 / Development Kit User’s Manual Development Board Implementation Comments PCI Express* Three x1 connectors One

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Getting Started 316704-001 / Development Kit User’s Manual 17 Development Board Implementation Comments Power Management ACPI Compliant S0

Strany 10 - Table 3. Acronyms

Getting Started 18 316704-001 / Development Kit User’s Manual Note: While every care was taken to ensure the latest versions of drivers were p

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Getting Started 316704-001 / Development Kit User’s Manual 19 VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The setup

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2 316704-001 / Development Kit User’s Manual INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE

Strany 13 - 1.5 Product Literature

Getting Started 20 316704-001 / Development Kit User’s Manual Other Devices and Adapters: The development board functions much like a standard

Strany 14 - 1.6 Related Documents

Getting Started 316704-001 / Development Kit User’s Manual 21 Note: Ensure that the processor has been locked into the socket by turning the

Strany 15 - 2 Getting Started

Theory of Operation 22 316704-001 / Development Kit User’s Manual 3 Theory of Operation 3.1 Block Diagram Figure 1. Development Board Block D

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Theory of Operation 316704-001 / Development Kit User’s Manual 23 chassis. Internal and rear panel system I/O connectors are described in Secti

Strany 17 - 2.3 Software Key Features

Theory of Operation 24 316704-001 / Development Kit User’s Manual • SDVO interface via PCI Express* x16 connector provides maximum display fle

Strany 18 - 2.4 Before You Begin

Theory of Operation 316704-001 / Development Kit User’s Manual 25 3.4.1.4 PCI Express x16 Slot The development board provides access to one x1

Strany 19 - Getting Started

Theory of Operation 26 316704-001 / Development Kit User’s Manual 3.4.2.3 On-Board LAN The development board has one RJ-45 interface – at conn

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Theory of Operation 316704-001 / Development Kit User’s Manual 27 connector at J5A1. Four ports are routed to USB front panel headers at J6H3 a

Strany 21 - 2.6 Configuring the BIOS

Theory of Operation 28 316704-001 / Development Kit User’s Manual Table 7. BIOS Location Strapping Options ICH8-M Signal GNT#0 SPI_CS1# BIOS L

Strany 22 - 3 Theory of Operation

Theory of Operation 316704-001 / Development Kit User’s Manual 29 3.4.3 POST Code Debugger A Port 80-83 Add-in card can be plugged into to the

Strany 23 - 3.3 Thermal Management

316704-001 / Development Kit User’s Manual 3 Contents 1 About This Manual ...

Strany 24 - 3.4.1.2 DMI

Theory of Operation 30 316704-001 / Development Kit User’s Manual State Description G0/S0/C3 Deep Sleep: DPSLP# signal active G0/S0/C4 Deeper

Strany 25 - 3.4.2 ICH8-M

Theory of Operation 316704-001 / Development Kit User’s Manual 31 Table 11. Sleep Signals and M-State Definition Signal SLP_S3# SLP_S4# S

Strany 26 - 3.4.2.6 USB Connectors

Theory of Operation 32 316704-001 / Development Kit User’s Manual Table 12. Development Board Voltage Rails Component/ Interface Voltage Plane

Strany 27 - 3.4.2.10 SPI

Theory of Operation 316704-001 / Development Kit User’s Manual 33 Component/ Interface Voltage Plane Supply Rail Reference Designator GMCH 1.

Strany 28 - 3.4.2.14 Thermal Monitoring

Theory of Operation 34 316704-001 / Development Kit User’s Manual Component/ Interface Voltage Plane Supply Rail Reference Designator Memory 1

Strany 29 - 3.6 Power Management States

Theory of Operation 316704-001 / Development Kit User’s Manual 35 Component/ Interface Voltage Plane Supply Rail Reference Designator Panel LV

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Theory of Operation 36 316704-001 / Development Kit User’s Manual Component/ Interface Voltage Plane Supply Rail Reference Designator System

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Hardware Reference 316704-001 / Development Kit User’s Manual 37 4 Hardware Reference This section provides reference information on the hardw

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Hardware Reference 38 316704-001 / Development Kit User’s Manual Table 13. Development Board Component Location Legend Reference Designator Fu

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Hardware Reference 316704-001 / Development Kit User’s Manual 39 Reference Designator Function J7J4 PATA Connector J8A1 Reserved J8A2 Reserved

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4 316704-001 / Development Kit User’s Manual Figures Figure 1. Development Board Block Diagram...

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Hardware Reference 40 316704-001 / Development Kit User’s Manual Figure 3. Back Panel Connector Locations n o p q

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Hardware Reference 316704-001 / Development Kit User’s Manual 41 Figure 4. D-Connector to Component Video Cable Figure 5. D-Connector to Compo

Strany 37 - 4 Hardware Reference

Hardware Reference 42 316704-001 / Development Kit User’s Manual The unsupported jumpers must remain in their default position or the operation

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Hardware Reference 316704-001 / Development Kit User’s Manual 43 Reference Designator Function Default Setting Optional Setting Override For

Strany 39 - 4.2 Back Panel Connectors

Hardware Reference 44 316704-001 / Development Kit User’s Manual Reference Designator Function Default Setting Optional Setting J3J1 Reserved

Strany 40 - 4.2.1 TV-Out D-Connector

Hardware Reference 316704-001 / Development Kit User’s Manual 45 Reference Designator Function Default Setting Optional Setting H8 Programmin

Strany 41 - 4.3 Configuration Settings

Hardware Reference 46 316704-001 / Development Kit User’s Manual 4.5 LEDs The development board has a number of LEDs. These LEDs provide statu

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Hardware Reference 316704-001 / Development Kit User’s Manual 47 Function Reference Designator VID 0 CR1B1 VID 1 CR1B2 VID 2 CR1B3 VID 3 CR

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Hardware Reference 48 316704-001 / Development Kit User’s Manual d. J9H2 (1-2) (default: 1-X), disable 1 Hz Clock. 4. Attach an ATX power sup

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Hardware Reference 316704-001 / Development Kit User’s Manual 49 Reference Designator Slot/Socket Description Detail J6H5 Front Panel Header

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316704-001 / Development Kit User’s Manual 5 Revision History Document Number Revision Number Description Revision Date 316704 001 Initial

Strany 46 - 4.5 LEDs

Hardware Reference 50 316704-001 / Development Kit User’s Manual Pin Description Pin Description A11 PERST# B11 WAKE# Key A12 GND B12 RSVD A

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Hardware Reference 316704-001 / Development Kit User’s Manual 51 Pin Description Pin Description A43 LANE 6 (R+) B43 GND A44 LANE 6 (R-)

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Hardware Reference 52 316704-001 / Development Kit User’s Manual Pin Description Pin Description A77 LANE 14 (R-) B77 GND A78 GND B78 LA

Strany 49 - 4.6.2.2 PCI Express* (x16)

Hardware Reference 316704-001 / Development Kit User’s Manual 53 Pin Description Pin Description A18 GND B18 GND End of x1 Connector A19 Reser

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Hardware Reference 54 316704-001 / Development Kit User’s Manual Pin Description Pin Description A50 Reserved B50 N/C A51 GND B51 N/C A52 N/C

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Hardware Reference 316704-001 / Development Kit User’s Manual 55 Table 20. MEC Slot (J6B2) Pin Description Pin Description A1 N/C B1 12 V A2

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Hardware Reference 56 316704-001 / Development Kit User’s Manual Pin Description Pin Description End of x4 Connector A33 Reserved B33 N/C A34

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Hardware Reference 316704-001 / Development Kit User’s Manual 57 Pin Description Pin Description A66 GND B66 SDVOB_Clk+ A67 GND B67 SDVOB_Clk

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Hardware Reference 58 316704-001 / Development Kit User’s Manual Pin Description Pin Description Key A12 GND B12 RSVD A13 REFCLK+ B13 GND A1

Strany 55 - Table 20. MEC Slot (J6B2)

Hardware Reference 316704-001 / Development Kit User’s Manual 59 4.6.2.6 SATA Pinout Up to three SATA devices may be supported by the SATA con

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About This Manual 6 316704-001 / Development Kit User’s Manual 1 About This Manual This user’s manual describes the use of the Intel® CoreTM 2

Strany 57 - 4.6.2.4 PCI Express* (x1)

Hardware Reference 60 316704-001 / Development Kit User’s Manual Connector J2B3 is used to power the CPU fan. Connectors J2C1 and J2F1 are not

Strany 58 - 4.6.2.5 IDE Connector

Hardware Reference 316704-001 / Development Kit User’s Manual 61 16 +V5 5 volt supply 4.6.2.9 USB Headers (J6H3, J6H4) The USB headers imple

Strany 59 - 4.6.2.7 Fan Connectors

Hardware Reference 62 316704-001 / Development Kit User’s Manual Appendix A . Heatsink Installation Instructions It is necessary for the Intel®

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Hardware Reference 316704-001 / Development Kit User’s Manual 63 Figure 10. Backplate Pins 4. Clean the die of the processor with isopropyl a

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Hardware Reference 64 316704-001 / Development Kit User’s Manual Figure 11. Applying the Thermal Grease 6. Pick up the heatsink and squeeze t

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Hardware Reference 316704-001 / Development Kit User’s Manual 65 7. While keeping the activation arm compressed, place the heatsink over the p

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Hardware Reference 66 316704-001 / Development Kit User’s Manual Figure 14. Plugging in the Fan Figure 15. Completed Assembly

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About This Manual 316704-001 / Development Kit User’s Manual 7 Table 1. Text Conventions Notation Definition # The pound symbol (#) appended t

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About This Manual 8 316704-001 / Development Kit User’s Manual 1.3 Glossary of Terms and Acronyms Table 2 defines conventions and terminology

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About This Manual 316704-001 / Development Kit User’s Manual 9 Term/Acronym Definition manufacturer’s conditions required for AC timing specifi

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