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9-6 Intel® PXA255 Processor Developer’s Manual
I
2
C Bus Interface Unit
Figure 9-3. START and STOP Conditions
Data byte
ACK/
NAK
ACK/
NAK
R/nWSTART Target Slave Address
ACK/
NAK
Data Byte
STOP
No START or STOP Condition
START Condition
STOP Condition
- Intel® PXA255 Processor 1
- Revision History 23
- Contents 24
- Introduction 1 25
- 1.2.1 Memory Controller 26
- C) Bus Interface Unit 28
- 1.2.12 GPIO 28
- 1.2.13 UARTs 28
- 1.2.14 Real-Time Clock (RTC) 29
- 1.2.15 OS Timers 29
- 1.2.17 Interrupt Control 29
- Introduction 30
- System Architecture 2 31
- Peripheral Bus 32
- Management 33
- 2.3 I/O Ordering 35
- 2.4 Semaphores 35
- 2.5 Interrupts 35
- 2.6 Reset 36
- 2.7 Internal Registers 37
- 2.10 Power Management 38
- 2.11 Pin List 38
- System Architecture 39
- 2.12 Memory Map 48
- Clocks and Power Manager 3 63
- 3.3 Clock Manager 64
- 3.3.1 32.768 kHz Oscillator 66
- 3.3.2 3.6864 MHz Oscillator 66
- 3.3.3 Core Phase Locked Loop 66
- 3.4 Resets and Power Modes 68
- 3.4.2 Watchdog Reset 69
- 3.4.3 GPIO Reset 70
- 3.4.4 Run Mode 71
- 3.4.5 Turbo Mode 71
- 3.4.6 Idle Mode 72
- 3.4.6.2 Behavior in Idle Mode 73
- 3.4.6.3 Exiting Idle Mode 73
- 3.4.8 33-MHz Idle Mode 75
- 3.4.9 Sleep Mode 77
- 3.4.9.3 Entering Sleep Mode 78
- 3.4.9.5 Exiting Sleep Mode 80
- 3.4.10 Power Mode Summary 82
- 3.5 Power Manager Registers 84
- PGSR1, PGSR2) 93
- • Hardware reset 95
- • Watchdog reset 95
- • Sleep mode 95
- • GPIO reset 95
- 3.6 Clocks Manager Registers 96
- Oscillator 103
- Clocks and Power Manager 104
- System Integration Unit 4 105
- System Integration Unit 107
- 4.2 Interrupt Controller 124
- Register (ICFP) 128
- 4.3 Real-Time Clock (RTC) 132
- 4.3.3 Trim Procedure 136
- – each time the operating 139
- 4.5 Pulse Width Modulator 142
- 4.5.1.1 Interdependencies 143
- 4.5.2 Register Descriptions 144
- • FDCYCLE 145
- • DCYCLE 145
- 4.6.1 GPIO Register Locations 148
- DMA Controller 5 151
- 5.1.1 DMAC Channels 152
- 5.1.2 Signal Descriptions 152
- 5.1.2.2 DMA_IRQ Signal 153
- 5.1.4 DMA Descriptors 155
- 5.1.4.2 Descriptor Fetch Mode 156
- 5.1.6 Read and Write Order 159
- 5.1.7 Byte Transfer Order 159
- 5.2 Transferring Data 161
- DMA Controller 163
- 5.2.4 Memory-to-Memory Moves 166
- 5.3 DMAC Registers 167
- 5.4 Examples 176
- Memory Controller 6 183
- 6.2 Functional Description 184
- 6.3 Memory System Examples 186
- Memory Controller 187
- 6.4 Memory Accesses 189
- 6.4.1 Reads and Writes 190
- 6.5.5 SDRAM Memory Options 200
- 6.5.6 SDRAM Command Overview 209
- 6.5.7 SDRAM Waveforms 210
- Figure 6-9. SDRAM_write 213
- 6.6.1.1 SMROM Memory Options 218
- CL = 5CL = 5RL = 2RL = 2 221
- 6.7.1 Static Memory Interface 224
- Register (SA1111CR) 226
- 6.7.4 ROM Interface 232
- MSC0[RDN] = 1, MSC0[RRR] = 1) 233
- MSC0[RDN] = 1, MSC0[RRR] = 0) 234
- 6.7.5 SRAM Interface Overview 235
- Variable Latency I/O writes 238
- 6.7.7 FLASH Memory Interface 240
- 6.8.3 16-Bit PC Card Overview 246
- 0ns 50ns 100ns 150ns 251
- 6.9 Companion Chip Interface 252
- 6.9.1.1 GPIO Reset 255
- 6.10.1 Alternate Booting 256
- 6.10.2 Boot Time Defaults 256
- Table 6-40. BOOT_DEF Bitmap 257
- 6.12 GPIO Reset Procedure 263
- LCD Controller 7 265
- 7.1.1 Features 266
- LCD Controller 267
- 7.2 LCD Controller Operation 268
- 7.3.1 Input FIFOs 269
- 7.3.2 Lookup Palette 270
- 7.3.4 Output FIFOs 272
- 7.3.6 DMA 273
- 7.4.1 External Palette Buffer 274
- 7.4.2 External Frame Buffer 275
- 7.5 Functional Timing 278
- ENB set to 1 280
- 7.6 Register Descriptions 281
- • DMA bus errors 282
- 7.6.5 LCD Controller DMA 296
- 8.1 Overview 311
- 8.2 Signal Description 311
- 8.3 Functional Description 312
- 8.4 Data Formats 312
- 8.4.1.2 SPI Format Details 314
- 8.6 Baud-Rate Generation 317
- 8.7 SSP Serial Port Registers 318
- 8.7.1.2 Frame Format (FRF) 320
- 8.7.2.3 Loop Back Mode (LBM) 322
- C Bus Interface Unit 9 331
- 9.3.1 Operational Blocks 333
- 9.3.2 I 333
- C Bus Interface Modes 333
- 9.3.3.1 START Condition 335
- 9.3.3.3 STOP Condition 335
- C Bus Interface Unit 336
- C Bus Operation 337
- C Acknowledge 338
- 9.4.4 Polling 339
- 9.4.5 Arbitration 339
- 9.4.5.1 SCL Arbitration 340
- 9.4.5.2 SDA Arbitration 340
- 9.4.6 Master Operations 342
- 9.4.7 Slave Operations 344
- 9.4.8 General Call Address 346
- • Sets the ISR[GCAD] bit 347
- • Sets the ISR[SAD] bit 347
- 9.5.1 Initialize Unit 348
- 9.5.3 Read n Bytes as a Slave 348
- 9.6.1 Initialize Unit 349
- 9.6.3 Read 1 Byte as a Master 350
- 9.7 Glitch Suppression Logic 351
- 9.8 Reset Conditions 351
- 9.9 Register Definitions 352
- C Control Register (ICR) 353
- for the following I 354
- C Status Register (ISR) 355
- UARTs 10 359
- 10.2 Overview 360
- 10.3 Signal Descriptions 361
- 10.4.1 Reset 363
- 10.4.5 DMA Requests 380
- 10.4.6.2 Operation 382
- 10.5 UART Register Summary 384
- 11.1 Signal Description 387
- 11.2 FICP Operation 387
- 11.2.1 4PPM Modulation 388
- 11.2.2 Frame Format 389
- 11.2.3 Address Field 389
- 11.2.4 Control Field 389
- 11.2.5 Data Field 389
- 11.2.6 CRC Field 390
- 11.2.7 Baud Rate Generation 390
- 11.2.8 Receive Operation 390
- 11.2.9 Transmit Operation 391
- 11.4 FICP Register Summary 402
- USB Device Controller 12 403
- 12.2 Device Configuration 404
- 12.3 USB Protocol 404
- 12.3.1 Signalling Levels 405
- 12.3.2 Bit Encoding 405
- 12.3.3 Field Formats 406
- 12.3.4 Packet Formats 407
- 12.3.5 Transaction Formats 408
- 12.3.6 UDC Device Requests 410
- 12.3.7 Configuration 411
- 12.4 UDC Hardware Connection 412
- (optional) 413
- 12.5 UDC Operation 414
- Status Stage 416
- 12.5.7.1 Software Enables DMA 419
- 12.6 UDC Register Definitions 423
- 12.6.1.1 UDC Enable (UDE) 424
- 12.6.2.1 ACK Control Mode 426
- 12.6.2.2 ACK Response Enable 426
- 12.6.3.3 Flush Tx FIFO (FTF) 428
- 12.6.3.5 Sent Stall (SST) 428
- 12.6.3.6 Force Stall (FST) 428
- 12.6.3.8 Setup Active (SA) 429
- 12.6.7.4 DMA Enable (DME) 436
- 12.6.7.5 Bits 5:4 Reserved 436
- 12.6.8.3 Flush Tx FIFO (FTF) 437
- 12.6.8.5 Sent STALL (SST) 438
- 12.6.8.6 Force STALL (FST) 438
- 12.6.8.7 Bit 6 Reserved 438
- USB Device Controller 451
- AC’97 Controller Unit 13 453
- 13.3 Signal Description 454
- OUTGOING STREAMS 456
- INCOMING STREAMS 456
- Data PhaseTag Phase 456
- SDATA_OUT 457
- 13.4.1.1 Slot 0: Tag Phase 458
- 13.4.1.7 Slots 6-11: Reserved 460
- 13.4.1.8 Slot 12: I/O Control 460
- 13.4.2.1 Slot 0: Tag Phase 461
- 13.5 AC-link Low Power Mode 464
- 13.5.2 Waking up the AC-link 465
- 13.6 ACUNIT Operation 466
- 13.6.1 Initialization 467
- AC’97 Controller Unit 468
- 13.6.2 Trailing bytes 469
- 13.8 Functional Description 470
- 13.8.2 Interrupts 471
- 13.8.3 Registers 471
- 13.9 AC’97 Register Summary 487
- Controller 14 489
- 14.2 Signal Descriptions 490
- 14.3 Controller Operation 491
- 14.3.4 Transmit FIFO Errors 493
- 14.3.5 Receive FIFO Errors 493
- 14.3.6 Trailing Bytes 493
- 14.5 Data Formats 494
- A8842-01 495
- A8843-01 495
- 14.6 Registers 496
- EFWR STRF Description 498
- Min Max Min Max 498
- Bits Name Description 501
- 14.7 Interrupts 503
- S Controller Register Summary 503
- (paddr(9:0) 504
- Register 504
- Description 504
- MultiMediaCard Controller 15 505
- Value Description 506
- 15.2.1 Signal Description 510
- 15.2.2 MMC Controller Reset 510
- 15.2.4 MMC and SPI Modes 510
- 15.2.4.1 MMC Mode 511
- 15.2.5 Error Detection 512
- 15.2.6 Interrupts 512
- 15.2.7 Clock Control 513
- 15.2.8 Data FIFOs 514
- • Receive 96 bytes of data: 515
- • Receive 98 bytes of data: 515
- • Receive 105 bytes: 515
- • Transmit 96 bytes of data: 516
- • Transmit 98 bytes of data: 516
- • Transmit 105 bytes: 516
- 15.2.8.4 DMA and Program I/O 516
- 15.3.2 Data Transfer 517
- 15.3.2.1 Block Data Write 518
- Time-out Delay 519
- MMC_RDTO[READ_TO]()128()× 519
- 15.3.3 Busy Sequence 520
- 15.3.4 SPI Functionality 521
- 15.4.1 Start and Stop Clock 521
- 15.4.2 Initialize 521
- 15.4.3 Enabling SPI Mode 521
- 15.4.5 Erase 522
- 15.4.7 Single Block Read 523
- 15.4.8 Multiple Block Write 524
- 15.4.9 Multiple Block Read 524
- 15.4.10 Stream Write 525
- 15.4.11 Stream Read 525
- 15.5 MMC Controller Registers 526
- 31:16 — reserved 532
- 31:10 — reserved 533
- MultiMediaCard Controller 536
- Table 15-17. MMC_CMD Register 537
- 15.5.16 MMC_RES FIFO 540
- 15.5.17 MMC_RXFIFO FIFO 540
- 15.5.18 MMC_TXFIFO FIFO 541
- Network SSP Serial Port 16 543
- 16.3 Signal Description 544
- 16.4 Operation 544
- 16.4.3 Data Formats 545
- A9650-01 547
- 16.4.3.2 SPI Protocol Details 548
- A9652-01 550
- 16.4.3.4 PSP Details 552
- Bit[0]Bit[1] 552
- Bit[N] Bit[0] Bit[N] 552
- Undefined Undefined Undefined 552
- A9523-02 553
- Symbol Definition Range Units 554
- 16.4.4 Hi-Z on SSPTXD 555
- A9975-01 556
- A9976-01 556
- UndefinedUndefinedUndefined 557
- T1 T2 T3 T4 558
- 16.4.5 FIFO Operation 559
- 16.4.6 Baud-Rate Generation 559
- 16.5 Register Descriptions 560
- Network SSP Serial Port 561
- Hardware UART 17 573
- 17.3 Signal Descriptions 575
- 17.4.1 Reset 576
- 17.4.2 FIFO Operation 576
- 17.4.3 Autoflow Control 579
- can be programmed by 580
- 17.4.5.1 Operation 580
- 17.5 Register Descriptions 582
- BaudRate 583
- 14.7456 MHz 583
- 16xDivisor() 583
- Bit Definitions 590
- Hardware UART 592
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